omap4.dtsi 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/bus/ti-sysc.h>
  6. #include <dt-bindings/clock/omap4.h>
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. #include <dt-bindings/pinctrl/omap.h>
  10. #include <dt-bindings/clock/omap4.h>
  11. / {
  12. compatible = "ti,omap4430", "ti,omap4";
  13. interrupt-parent = <&wakeupgen>;
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. chosen { };
  17. aliases {
  18. i2c0 = &i2c1;
  19. i2c1 = &i2c2;
  20. i2c2 = &i2c3;
  21. i2c3 = &i2c4;
  22. serial0 = &uart1;
  23. serial1 = &uart2;
  24. serial2 = &uart3;
  25. serial3 = &uart4;
  26. };
  27. cpus {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. cpu@0 {
  31. compatible = "arm,cortex-a9";
  32. device_type = "cpu";
  33. next-level-cache = <&L2>;
  34. reg = <0x0>;
  35. clocks = <&dpll_mpu_ck>;
  36. clock-names = "cpu";
  37. clock-latency = <300000>; /* From omap-cpufreq driver */
  38. };
  39. cpu@1 {
  40. compatible = "arm,cortex-a9";
  41. device_type = "cpu";
  42. next-level-cache = <&L2>;
  43. reg = <0x1>;
  44. };
  45. };
  46. /*
  47. * Note that 4430 needs cross trigger interface (CTI) supported
  48. * before we can configure the interrupts. This means sampling
  49. * events are not supported for pmu. Note that 4460 does not use
  50. * CTI, see also 4460.dtsi.
  51. */
  52. pmu {
  53. compatible = "arm,cortex-a9-pmu";
  54. ti,hwmods = "debugss";
  55. };
  56. gic: interrupt-controller@48241000 {
  57. compatible = "arm,cortex-a9-gic";
  58. interrupt-controller;
  59. #interrupt-cells = <3>;
  60. reg = <0x48241000 0x1000>,
  61. <0x48240100 0x0100>;
  62. interrupt-parent = <&gic>;
  63. };
  64. L2: l2-cache-controller@48242000 {
  65. compatible = "arm,pl310-cache";
  66. reg = <0x48242000 0x1000>;
  67. cache-unified;
  68. cache-level = <2>;
  69. };
  70. local-timer@48240600 {
  71. compatible = "arm,cortex-a9-twd-timer";
  72. clocks = <&mpu_periphclk>;
  73. reg = <0x48240600 0x20>;
  74. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  75. interrupt-parent = <&gic>;
  76. };
  77. wakeupgen: interrupt-controller@48281000 {
  78. compatible = "ti,omap4-wugen-mpu";
  79. interrupt-controller;
  80. #interrupt-cells = <3>;
  81. reg = <0x48281000 0x1000>;
  82. interrupt-parent = <&gic>;
  83. };
  84. /*
  85. * The soc node represents the soc top level view. It is used for IPs
  86. * that are not memory mapped in the MPU view or for the MPU itself.
  87. */
  88. soc {
  89. compatible = "ti,omap-infra";
  90. mpu {
  91. compatible = "ti,omap4-mpu";
  92. ti,hwmods = "mpu";
  93. sram = <&ocmcram>;
  94. };
  95. dsp {
  96. compatible = "ti,omap3-c64";
  97. };
  98. iva {
  99. compatible = "ti,ivahd";
  100. ti,hwmods = "iva";
  101. };
  102. };
  103. /*
  104. * XXX: Use a flat representation of the OMAP4 interconnect.
  105. * The real OMAP interconnect network is quite complex.
  106. * Since it will not bring real advantage to represent that in DT for
  107. * the moment, just use a fake OCP bus entry to represent the whole bus
  108. * hierarchy.
  109. */
  110. ocp {
  111. compatible = "ti,omap4-l3-noc", "simple-bus";
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. ranges;
  115. ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  116. reg = <0x44000000 0x1000>,
  117. <0x44800000 0x2000>,
  118. <0x45000000 0x1000>;
  119. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  120. <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  121. l4_wkup: interconnect@4a300000 {
  122. };
  123. l4_cfg: interconnect@4a000000 {
  124. };
  125. l4_per: interconnect@48000000 {
  126. };
  127. l4_abe: interconnect@40100000 {
  128. };
  129. ocmcram: sram@40304000 {
  130. compatible = "mmio-sram";
  131. reg = <0x40304000 0xa000>; /* 40k */
  132. };
  133. gpmc: gpmc@50000000 {
  134. compatible = "ti,omap4430-gpmc";
  135. reg = <0x50000000 0x1000>;
  136. #address-cells = <2>;
  137. #size-cells = <1>;
  138. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  139. dmas = <&sdma 4>;
  140. dma-names = "rxtx";
  141. gpmc,num-cs = <8>;
  142. gpmc,num-waitpins = <4>;
  143. ti,hwmods = "gpmc";
  144. ti,no-idle-on-init;
  145. clocks = <&l3_div_ck>;
  146. clock-names = "fck";
  147. interrupt-controller;
  148. #interrupt-cells = <2>;
  149. gpio-controller;
  150. #gpio-cells = <2>;
  151. };
  152. target-module@52000000 {
  153. compatible = "ti,sysc-omap4", "ti,sysc";
  154. ti,hwmods = "iss";
  155. reg = <0x52000000 0x4>,
  156. <0x52000010 0x4>;
  157. reg-names = "rev", "sysc";
  158. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  159. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  160. <SYSC_IDLE_NO>,
  161. <SYSC_IDLE_SMART>,
  162. <SYSC_IDLE_SMART_WKUP>;
  163. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  164. <SYSC_IDLE_NO>,
  165. <SYSC_IDLE_SMART>,
  166. <SYSC_IDLE_SMART_WKUP>;
  167. ti,sysc-delay-us = <2>;
  168. clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
  169. clock-names = "fck";
  170. #address-cells = <1>;
  171. #size-cells = <1>;
  172. ranges = <0 0x52000000 0x1000000>;
  173. /* No child device binding, driver in staging */
  174. };
  175. target-module@55082000 {
  176. compatible = "ti,sysc-omap2", "ti,sysc";
  177. reg = <0x55082000 0x4>,
  178. <0x55082010 0x4>,
  179. <0x55082014 0x4>;
  180. reg-names = "rev", "sysc", "syss";
  181. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  182. <SYSC_IDLE_NO>,
  183. <SYSC_IDLE_SMART>;
  184. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  185. SYSC_OMAP2_SOFTRESET |
  186. SYSC_OMAP2_AUTOIDLE)>;
  187. clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
  188. clock-names = "fck";
  189. resets = <&prm_core 2>;
  190. reset-names = "rstctrl";
  191. ranges = <0x0 0x55082000 0x100>;
  192. #size-cells = <1>;
  193. #address-cells = <1>;
  194. mmu_ipu: mmu@0 {
  195. compatible = "ti,omap4-iommu";
  196. reg = <0x0 0x100>;
  197. interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  198. #iommu-cells = <0>;
  199. ti,iommu-bus-err-back;
  200. };
  201. };
  202. target-module@4012c000 {
  203. compatible = "ti,sysc-omap4", "ti,sysc";
  204. reg = <0x4012c000 0x4>,
  205. <0x4012c010 0x4>;
  206. reg-names = "rev", "sysc";
  207. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  208. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  209. <SYSC_IDLE_NO>,
  210. <SYSC_IDLE_SMART>,
  211. <SYSC_IDLE_SMART_WKUP>;
  212. clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
  213. clock-names = "fck";
  214. #address-cells = <1>;
  215. #size-cells = <1>;
  216. ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
  217. <0x4902c000 0x4902c000 0x1000>; /* L3 */
  218. /* No child device binding or driver in mainline */
  219. };
  220. dmm@4e000000 {
  221. compatible = "ti,omap4-dmm";
  222. reg = <0x4e000000 0x800>;
  223. interrupts = <0 113 0x4>;
  224. ti,hwmods = "dmm";
  225. };
  226. emif1: emif@4c000000 {
  227. compatible = "ti,emif-4d";
  228. reg = <0x4c000000 0x100>;
  229. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  230. ti,hwmods = "emif1";
  231. ti,no-idle-on-init;
  232. phy-type = <1>;
  233. hw-caps-read-idle-ctrl;
  234. hw-caps-ll-interface;
  235. hw-caps-temp-alert;
  236. };
  237. emif2: emif@4d000000 {
  238. compatible = "ti,emif-4d";
  239. reg = <0x4d000000 0x100>;
  240. interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  241. ti,hwmods = "emif2";
  242. ti,no-idle-on-init;
  243. phy-type = <1>;
  244. hw-caps-read-idle-ctrl;
  245. hw-caps-ll-interface;
  246. hw-caps-temp-alert;
  247. };
  248. aes1_target: target-module@4b501000 {
  249. compatible = "ti,sysc-omap2", "ti,sysc";
  250. reg = <0x4b501080 0x4>,
  251. <0x4b501084 0x4>,
  252. <0x4b501088 0x4>;
  253. reg-names = "rev", "sysc", "syss";
  254. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  255. SYSC_OMAP2_AUTOIDLE)>;
  256. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  257. <SYSC_IDLE_NO>,
  258. <SYSC_IDLE_SMART>,
  259. <SYSC_IDLE_SMART_WKUP>;
  260. ti,syss-mask = <1>;
  261. /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
  262. clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
  263. clock-names = "fck";
  264. #address-cells = <1>;
  265. #size-cells = <1>;
  266. ranges = <0x0 0x4b501000 0x1000>;
  267. aes1: aes@0 {
  268. compatible = "ti,omap4-aes";
  269. reg = <0 0xa0>;
  270. interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  271. dmas = <&sdma 111>, <&sdma 110>;
  272. dma-names = "tx", "rx";
  273. };
  274. };
  275. aes2_target: target-module@4b701000 {
  276. compatible = "ti,sysc-omap2", "ti,sysc";
  277. reg = <0x4b701080 0x4>,
  278. <0x4b701084 0x4>,
  279. <0x4b701088 0x4>;
  280. reg-names = "rev", "sysc", "syss";
  281. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  282. SYSC_OMAP2_AUTOIDLE)>;
  283. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  284. <SYSC_IDLE_NO>,
  285. <SYSC_IDLE_SMART>,
  286. <SYSC_IDLE_SMART_WKUP>;
  287. ti,syss-mask = <1>;
  288. /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
  289. clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
  290. clock-names = "fck";
  291. #address-cells = <1>;
  292. #size-cells = <1>;
  293. ranges = <0x0 0x4b701000 0x1000>;
  294. aes2: aes@0 {
  295. compatible = "ti,omap4-aes";
  296. reg = <0 0xa0>;
  297. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  298. dmas = <&sdma 114>, <&sdma 113>;
  299. dma-names = "tx", "rx";
  300. };
  301. };
  302. sham_target: target-module@4b100000 {
  303. compatible = "ti,sysc-omap3-sham", "ti,sysc";
  304. reg = <0x4b100100 0x4>,
  305. <0x4b100110 0x4>,
  306. <0x4b100114 0x4>;
  307. reg-names = "rev", "sysc", "syss";
  308. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  309. SYSC_OMAP2_AUTOIDLE)>;
  310. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  311. <SYSC_IDLE_NO>,
  312. <SYSC_IDLE_SMART>;
  313. ti,syss-mask = <1>;
  314. /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
  315. clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
  316. clock-names = "fck";
  317. #address-cells = <1>;
  318. #size-cells = <1>;
  319. ranges = <0x0 0x4b100000 0x1000>;
  320. sham: sham@0 {
  321. compatible = "ti,omap4-sham";
  322. reg = <0 0x300>;
  323. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  324. dmas = <&sdma 119>;
  325. dma-names = "rx";
  326. };
  327. };
  328. abb_mpu: regulator-abb-mpu {
  329. compatible = "ti,abb-v2";
  330. regulator-name = "abb_mpu";
  331. #address-cells = <0>;
  332. #size-cells = <0>;
  333. ti,tranxdone-status-mask = <0x80>;
  334. clocks = <&sys_clkin_ck>;
  335. ti,settling-time = <50>;
  336. ti,clock-cycles = <16>;
  337. status = "disabled";
  338. };
  339. abb_iva: regulator-abb-iva {
  340. compatible = "ti,abb-v2";
  341. regulator-name = "abb_iva";
  342. #address-cells = <0>;
  343. #size-cells = <0>;
  344. ti,tranxdone-status-mask = <0x80000000>;
  345. clocks = <&sys_clkin_ck>;
  346. ti,settling-time = <50>;
  347. ti,clock-cycles = <16>;
  348. status = "disabled";
  349. };
  350. target-module@56000000 {
  351. compatible = "ti,sysc-omap4", "ti,sysc";
  352. reg = <0x5600fe00 0x4>,
  353. <0x5600fe10 0x4>;
  354. reg-names = "rev", "sysc";
  355. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  356. <SYSC_IDLE_NO>,
  357. <SYSC_IDLE_SMART>,
  358. <SYSC_IDLE_SMART_WKUP>;
  359. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  360. <SYSC_IDLE_NO>,
  361. <SYSC_IDLE_SMART>,
  362. <SYSC_IDLE_SMART_WKUP>;
  363. clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
  364. clock-names = "fck";
  365. #address-cells = <1>;
  366. #size-cells = <1>;
  367. ranges = <0 0x56000000 0x2000000>;
  368. /*
  369. * Closed source PowerVR driver, no child device
  370. * binding or driver in mainline
  371. */
  372. };
  373. /*
  374. * DSS is only using l3 mapping without l4 as noted in the TRM
  375. * "10.1.3 DSS Register Manual" for omap4460.
  376. */
  377. target-module@58000000 {
  378. compatible = "ti,sysc-omap2", "ti,sysc";
  379. reg = <0x58000000 4>,
  380. <0x58000014 4>;
  381. reg-names = "rev", "syss";
  382. ti,syss-mask = <1>;
  383. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
  384. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
  385. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
  386. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
  387. clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
  388. #address-cells = <1>;
  389. #size-cells = <1>;
  390. ranges = <0 0x58000000 0x1000000>;
  391. dss: dss@0 {
  392. compatible = "ti,omap4-dss";
  393. reg = <0 0x80>;
  394. status = "disabled";
  395. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
  396. clock-names = "fck";
  397. #address-cells = <1>;
  398. #size-cells = <1>;
  399. ranges = <0 0 0x1000000>;
  400. target-module@1000 {
  401. compatible = "ti,sysc-omap2", "ti,sysc";
  402. reg = <0x1000 0x4>,
  403. <0x1010 0x4>,
  404. <0x1014 0x4>;
  405. reg-names = "rev", "sysc", "syss";
  406. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  407. <SYSC_IDLE_NO>,
  408. <SYSC_IDLE_SMART>;
  409. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  410. <SYSC_IDLE_NO>,
  411. <SYSC_IDLE_SMART>;
  412. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  413. SYSC_OMAP2_ENAWAKEUP |
  414. SYSC_OMAP2_SOFTRESET |
  415. SYSC_OMAP2_AUTOIDLE)>;
  416. ti,syss-mask = <1>;
  417. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
  418. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
  419. clock-names = "fck", "sys_clk";
  420. #address-cells = <1>;
  421. #size-cells = <1>;
  422. ranges = <0 0x1000 0x1000>;
  423. dispc@0 {
  424. compatible = "ti,omap4-dispc";
  425. reg = <0 0x1000>;
  426. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  427. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
  428. clock-names = "fck";
  429. };
  430. };
  431. target-module@2000 {
  432. compatible = "ti,sysc-omap2", "ti,sysc";
  433. reg = <0x2000 0x4>,
  434. <0x2010 0x4>,
  435. <0x2014 0x4>;
  436. reg-names = "rev", "sysc", "syss";
  437. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  438. <SYSC_IDLE_NO>,
  439. <SYSC_IDLE_SMART>;
  440. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  441. SYSC_OMAP2_AUTOIDLE)>;
  442. ti,syss-mask = <1>;
  443. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
  444. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
  445. clock-names = "fck", "sys_clk";
  446. #address-cells = <1>;
  447. #size-cells = <1>;
  448. ranges = <0 0x2000 0x1000>;
  449. rfbi: encoder@0 {
  450. reg = <0 0x1000>;
  451. status = "disabled";
  452. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
  453. clock-names = "fck", "ick";
  454. };
  455. };
  456. target-module@3000 {
  457. compatible = "ti,sysc-omap2", "ti,sysc";
  458. reg = <0x3000 0x4>;
  459. reg-names = "rev";
  460. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
  461. clock-names = "sys_clk";
  462. #address-cells = <1>;
  463. #size-cells = <1>;
  464. ranges = <0 0x3000 0x1000>;
  465. venc: encoder@0 {
  466. compatible = "ti,omap4-venc";
  467. reg = <0 0x1000>;
  468. status = "disabled";
  469. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
  470. clock-names = "fck";
  471. };
  472. };
  473. target-module@4000 {
  474. compatible = "ti,sysc-omap2", "ti,sysc";
  475. reg = <0x4000 0x4>,
  476. <0x4010 0x4>,
  477. <0x4014 0x4>;
  478. reg-names = "rev", "sysc", "syss";
  479. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  480. <SYSC_IDLE_NO>,
  481. <SYSC_IDLE_SMART>;
  482. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  483. SYSC_OMAP2_ENAWAKEUP |
  484. SYSC_OMAP2_SOFTRESET |
  485. SYSC_OMAP2_AUTOIDLE)>;
  486. ti,syss-mask = <1>;
  487. #address-cells = <1>;
  488. #size-cells = <1>;
  489. ranges = <0 0x4000 0x1000>;
  490. dsi1: encoder@0 {
  491. compatible = "ti,omap4-dsi";
  492. reg = <0 0x200>,
  493. <0x200 0x40>,
  494. <0x300 0x20>;
  495. reg-names = "proto", "phy", "pll";
  496. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  497. status = "disabled";
  498. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
  499. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
  500. clock-names = "fck", "sys_clk";
  501. };
  502. };
  503. target-module@5000 {
  504. compatible = "ti,sysc-omap2", "ti,sysc";
  505. reg = <0x5000 0x4>,
  506. <0x5010 0x4>,
  507. <0x5014 0x4>;
  508. reg-names = "rev", "sysc", "syss";
  509. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  510. <SYSC_IDLE_NO>,
  511. <SYSC_IDLE_SMART>;
  512. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  513. SYSC_OMAP2_ENAWAKEUP |
  514. SYSC_OMAP2_SOFTRESET |
  515. SYSC_OMAP2_AUTOIDLE)>;
  516. ti,syss-mask = <1>;
  517. #address-cells = <1>;
  518. #size-cells = <1>;
  519. ranges = <0 0x5000 0x1000>;
  520. dsi2: encoder@0 {
  521. compatible = "ti,omap4-dsi";
  522. reg = <0 0x200>,
  523. <0x200 0x40>,
  524. <0x300 0x20>;
  525. reg-names = "proto", "phy", "pll";
  526. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  527. status = "disabled";
  528. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
  529. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
  530. clock-names = "fck", "sys_clk";
  531. };
  532. };
  533. target-module@6000 {
  534. compatible = "ti,sysc-omap4", "ti,sysc";
  535. reg = <0x6000 0x4>,
  536. <0x6010 0x4>;
  537. reg-names = "rev", "sysc";
  538. /*
  539. * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
  540. * but HDMI audio will fail with them.
  541. */
  542. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  543. <SYSC_IDLE_NO>;
  544. ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
  545. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
  546. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
  547. clock-names = "fck", "dss_clk";
  548. #address-cells = <1>;
  549. #size-cells = <1>;
  550. ranges = <0 0x6000 0x2000>;
  551. hdmi: encoder@0 {
  552. compatible = "ti,omap4-hdmi";
  553. reg = <0 0x200>,
  554. <0x200 0x100>,
  555. <0x300 0x100>,
  556. <0x400 0x1000>;
  557. reg-names = "wp", "pll", "phy", "core";
  558. interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  559. status = "disabled";
  560. clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
  561. <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
  562. clock-names = "fck", "sys_clk";
  563. dmas = <&sdma 76>;
  564. dma-names = "audio_tx";
  565. };
  566. };
  567. };
  568. };
  569. };
  570. };
  571. #include "omap4-l4.dtsi"
  572. #include "omap4-l4-abe.dtsi"
  573. #include "omap44xx-clocks.dtsi"
  574. &prm {
  575. prm_tesla: prm@400 {
  576. compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
  577. reg = <0x400 0x100>;
  578. #reset-cells = <1>;
  579. };
  580. prm_core: prm@700 {
  581. compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
  582. reg = <0x700 0x100>;
  583. #reset-cells = <1>;
  584. };
  585. prm_ivahd: prm@f00 {
  586. compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
  587. reg = <0xf00 0x100>;
  588. #reset-cells = <1>;
  589. };
  590. prm_device: prm@1b00 {
  591. compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
  592. reg = <0x1b00 0x40>;
  593. #reset-cells = <1>;
  594. };
  595. };