uec.h 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #ifndef __UEC_H__
  9. #define __UEC_H__
  10. #include "uccf.h"
  11. #include <fsl_qe.h>
  12. #include <phy.h>
  13. #define MAX_TX_THREADS 8
  14. #define MAX_RX_THREADS 8
  15. #define MAX_TX_QUEUES 8
  16. #define MAX_RX_QUEUES 8
  17. #define MAX_PREFETCHED_BDS 4
  18. #define MAX_IPH_OFFSET_ENTRY 8
  19. #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
  20. #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
  21. /* UEC UPSMR (Protocol Specific Mode Register)
  22. */
  23. #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
  24. #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
  25. #define UPSMR_PRO 0x00400000 /* Promiscuous */
  26. #define UPSMR_CAP 0x00200000 /* CAM polarity */
  27. #define UPSMR_RSH 0x00100000 /* Receive Short Frames */
  28. #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
  29. #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
  30. #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
  31. #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
  32. #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
  33. #define UPSMR_CAM 0x00000400 /* CAM Address Matching */
  34. #define UPSMR_BRO 0x00000200 /* Broadcast Address */
  35. #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
  36. #define UPSMR_SGMM 0x00000020 /* SGMII mode */
  37. #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
  38. /* UEC MACCFG1 (MAC Configuration 1 Register)
  39. */
  40. #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
  41. #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
  42. #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
  43. #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
  44. #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
  45. #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
  46. #define MACCFG1_INIT_VALUE (0)
  47. /* UEC MACCFG2 (MAC Configuration 2 Register)
  48. */
  49. #define MACCFG2_PREL 0x00007000
  50. #define MACCFG2_PREL_SHIFT (31 - 19)
  51. #define MACCFG2_PREL_MASK 0x0000f000
  52. #define MACCFG2_SRP 0x00000080
  53. #define MACCFG2_STP 0x00000040
  54. #define MACCFG2_RESERVED_1 0x00000020 /* must be set */
  55. #define MACCFG2_LC 0x00000010 /* Length Check */
  56. #define MACCFG2_MPE 0x00000008
  57. #define MACCFG2_FDX 0x00000001 /* Full Duplex */
  58. #define MACCFG2_FDX_MASK 0x00000001
  59. #define MACCFG2_PAD_CRC 0x00000004
  60. #define MACCFG2_CRC_EN 0x00000002
  61. #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
  62. #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
  63. #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
  64. #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
  65. #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
  66. #define MACCFG2_INTERFACE_MODE_MASK 0x00000300
  67. #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
  68. MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
  69. /* UEC Event Register */
  70. #define UCCE_MPD 0x80000000
  71. #define UCCE_SCAR 0x40000000
  72. #define UCCE_GRA 0x20000000
  73. #define UCCE_CBPR 0x10000000
  74. #define UCCE_BSY 0x08000000
  75. #define UCCE_RXC 0x04000000
  76. #define UCCE_TXC 0x02000000
  77. #define UCCE_TXE 0x01000000
  78. #define UCCE_TXB7 0x00800000
  79. #define UCCE_TXB6 0x00400000
  80. #define UCCE_TXB5 0x00200000
  81. #define UCCE_TXB4 0x00100000
  82. #define UCCE_TXB3 0x00080000
  83. #define UCCE_TXB2 0x00040000
  84. #define UCCE_TXB1 0x00020000
  85. #define UCCE_TXB0 0x00010000
  86. #define UCCE_RXB7 0x00008000
  87. #define UCCE_RXB6 0x00004000
  88. #define UCCE_RXB5 0x00002000
  89. #define UCCE_RXB4 0x00001000
  90. #define UCCE_RXB3 0x00000800
  91. #define UCCE_RXB2 0x00000400
  92. #define UCCE_RXB1 0x00000200
  93. #define UCCE_RXB0 0x00000100
  94. #define UCCE_RXF7 0x00000080
  95. #define UCCE_RXF6 0x00000040
  96. #define UCCE_RXF5 0x00000020
  97. #define UCCE_RXF4 0x00000010
  98. #define UCCE_RXF3 0x00000008
  99. #define UCCE_RXF2 0x00000004
  100. #define UCCE_RXF1 0x00000002
  101. #define UCCE_RXF0 0x00000001
  102. #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
  103. UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
  104. #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
  105. UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
  106. #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
  107. UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
  108. #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
  109. UCCE_RXC | UCCE_TXC | UCCE_TXE)
  110. /* UEC TEMODR Register */
  111. #define TEMODER_SCHEDULER_ENABLE 0x2000
  112. #define TEMODER_IP_CHECKSUM_GENERATE 0x0400
  113. #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
  114. #define TEMODER_RMON_STATISTICS 0x0100
  115. #define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15)
  116. #define TEMODER_INIT_VALUE 0xc000
  117. /* UEC REMODR Register */
  118. #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
  119. #define REMODER_RX_EXTENDED_FEATURES 0x80000000
  120. #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9)
  121. #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10)
  122. #define REMODER_RX_QOS_MODE_SHIFT (31 - 15)
  123. #define REMODER_RMON_STATISTICS 0x00001000
  124. #define REMODER_RX_EXTENDED_FILTERING 0x00000800
  125. #define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23)
  126. #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
  127. #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
  128. #define REMODER_IP_CHECKSUM_CHECK 0x00000002
  129. #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
  130. #define REMODER_INIT_VALUE 0
  131. /* BMRx - Bus Mode Register */
  132. #define BMR_GLB 0x20
  133. #define BMR_BO_BE 0x10
  134. #define BMR_DTB_SECONDARY_BUS 0x02
  135. #define BMR_BDB_SECONDARY_BUS 0x01
  136. #define BMR_SHIFT 24
  137. #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
  138. /* UEC UCCS (Ethernet Status Register)
  139. */
  140. #define UCCS_BPR 0x02
  141. #define UCCS_PAU 0x02
  142. #define UCCS_MPD 0x01
  143. /* UEC MIIMCFG (MII Management Configuration Register)
  144. */
  145. #define MIIMCFG_RESET_MANAGEMENT 0x80000000
  146. #define MIIMCFG_NO_PREAMBLE 0x00000010
  147. #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
  148. #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
  149. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
  150. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
  151. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
  152. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
  153. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
  154. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
  155. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
  156. #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
  157. MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
  158. /* UEC MIIMCOM (MII Management Command Register)
  159. */
  160. #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
  161. #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
  162. /* UEC MIIMADD (MII Management Address Register)
  163. */
  164. #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
  165. #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
  166. /* UEC MIIMCON (MII Management Control Register)
  167. */
  168. #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
  169. #define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
  170. /* UEC MIIMIND (MII Management Indicator Register)
  171. */
  172. #define MIIMIND_NOT_VALID 0x00000004
  173. #define MIIMIND_SCAN 0x00000002
  174. #define MIIMIND_BUSY 0x00000001
  175. /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
  176. */
  177. #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
  178. #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
  179. /* UEC UESCR (Ethernet Statistics Control Register)
  180. */
  181. #define UESCR_AUTOZ 0x8000
  182. #define UESCR_CLRCNT 0x4000
  183. #define UESCR_MAXCOV_SHIFT (15 - 7)
  184. #define UESCR_SCOV_SHIFT (15 - 15)
  185. /****** Tx data struct collection ******/
  186. /* Tx thread data, each Tx thread has one this struct. */
  187. struct uec_thread_data_tx {
  188. u8 res0[136];
  189. } __packed;
  190. /* Tx thread parameter, each Tx thread has one this struct. */
  191. struct uec_thread_tx_pram {
  192. u8 res0[64];
  193. } __packed;
  194. /* Send queue queue-descriptor, each Tx queue has one this QD */
  195. struct uec_send_queue_qd {
  196. u32 bd_ring_base; /* pointer to BD ring base address */
  197. u8 res0[0x8];
  198. u32 last_bd_completed_address; /* last entry in BD ring */
  199. u8 res1[0x30];
  200. } __packed;
  201. /* Send queue memory region */
  202. struct uec_send_queue_mem_region {
  203. struct uec_send_queue_qd sqqd[MAX_TX_QUEUES];
  204. } __packed;
  205. /* Scheduler struct */
  206. struct uec_scheduler {
  207. u16 cpucount0; /* CPU packet counter */
  208. u16 cpucount1; /* CPU packet counter */
  209. u16 cecount0; /* QE packet counter */
  210. u16 cecount1; /* QE packet counter */
  211. u16 cpucount2; /* CPU packet counter */
  212. u16 cpucount3; /* CPU packet counter */
  213. u16 cecount2; /* QE packet counter */
  214. u16 cecount3; /* QE packet counter */
  215. u16 cpucount4; /* CPU packet counter */
  216. u16 cpucount5; /* CPU packet counter */
  217. u16 cecount4; /* QE packet counter */
  218. u16 cecount5; /* QE packet counter */
  219. u16 cpucount6; /* CPU packet counter */
  220. u16 cpucount7; /* CPU packet counter */
  221. u16 cecount6; /* QE packet counter */
  222. u16 cecount7; /* QE packet counter */
  223. u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
  224. u32 rtsrshadow; /* temporary variable handled by QE */
  225. u32 time; /* temporary variable handled by QE */
  226. u32 ttl; /* temporary variable handled by QE */
  227. u32 mblinterval; /* max burst length interval */
  228. u16 nortsrbytetime; /* normalized value of byte time in tsr units */
  229. u8 fracsiz;
  230. u8 res0[1];
  231. u8 strictpriorityq; /* Strict Priority Mask register */
  232. u8 txasap; /* Transmit ASAP register */
  233. u8 extrabw; /* Extra BandWidth register */
  234. u8 oldwfqmask; /* temporary variable handled by QE */
  235. u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
  236. u32 minw; /* temporary variable handled by QE */
  237. u8 res1[0x70 - 0x64];
  238. } __packed;
  239. /* Tx firmware counters */
  240. struct uec_tx_firmware_statistics_pram {
  241. u32 sicoltx; /* single collision */
  242. u32 mulcoltx; /* multiple collision */
  243. u32 latecoltxfr; /* late collision */
  244. u32 frabortduecol; /* frames aborted due to tx collision */
  245. u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
  246. u32 carriersenseertx; /* carrier sense error */
  247. u32 frtxok; /* frames transmitted OK */
  248. u32 txfrexcessivedefer;
  249. u32 txpkts256; /* total packets(including bad) 256~511 B */
  250. u32 txpkts512; /* total packets(including bad) 512~1023B */
  251. u32 txpkts1024; /* total packets(including bad) 1024~1518B */
  252. u32 txpktsjumbo; /* total packets(including bad) >1024 */
  253. } __packed;
  254. /* Tx global parameter table */
  255. struct uec_tx_global_pram {
  256. u16 temoder;
  257. u8 res0[0x38 - 0x02];
  258. u32 sqptr;
  259. u32 schedulerbasepointer;
  260. u32 txrmonbaseptr;
  261. u32 tstate;
  262. u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
  263. u32 vtagtable[0x8];
  264. u32 tqptr;
  265. u8 res2[0x80 - 0x74];
  266. } __packed;
  267. /****** Rx data struct collection ******/
  268. /* Rx thread data, each Rx thread has one this struct. */
  269. struct uec_thread_data_rx {
  270. u8 res0[40];
  271. } __packed;
  272. /* Rx thread parameter, each Rx thread has one this struct. */
  273. struct uec_thread_rx_pram {
  274. u8 res0[128];
  275. } __packed;
  276. /* Rx firmware counters */
  277. struct uec_rx_firmware_statistics_pram {
  278. u32 frrxfcser; /* frames with crc error */
  279. u32 fraligner; /* frames with alignment error */
  280. u32 inrangelenrxer; /* in range length error */
  281. u32 outrangelenrxer; /* out of range length error */
  282. u32 frtoolong; /* frame too long */
  283. u32 runt; /* runt */
  284. u32 verylongevent; /* very long event */
  285. u32 symbolerror; /* symbol error */
  286. u32 dropbsy; /* drop because of BD not ready */
  287. u8 res0[0x8];
  288. u32 mismatchdrop; /* drop because of MAC filtering */
  289. u32 underpkts; /* total frames less than 64 octets */
  290. u32 pkts256; /* total frames(including bad)256~511 B */
  291. u32 pkts512; /* total frames(including bad)512~1023 B */
  292. u32 pkts1024; /* total frames(including bad)1024~1518 B */
  293. u32 pktsjumbo; /* total frames(including bad) >1024 B */
  294. u32 frlossinmacer;
  295. u32 pausefr; /* pause frames */
  296. u8 res1[0x4];
  297. u32 removevlan;
  298. u32 replacevlan;
  299. u32 insertvlan;
  300. } __packed;
  301. /* Rx interrupt coalescing entry, each Rx queue has one this entry. */
  302. struct uec_rx_interrupt_coalescing_entry {
  303. u32 maxvalue;
  304. u32 counter;
  305. } __packed;
  306. struct uec_rx_interrupt_coalescing_table {
  307. struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES];
  308. } __packed;
  309. /* RxBD queue entry, each Rx queue has one this entry. */
  310. struct uec_rx_bd_queues_entry {
  311. u32 bdbaseptr; /* BD base pointer */
  312. u32 bdptr; /* BD pointer */
  313. u32 externalbdbaseptr; /* external BD base pointer */
  314. u32 externalbdptr; /* external BD pointer */
  315. } __packed;
  316. /* Rx global parameter table */
  317. struct uec_rx_global_pram {
  318. u32 remoder; /* ethernet mode reg. */
  319. u32 rqptr; /* base pointer to the Rx Queues */
  320. u32 res0[0x1];
  321. u8 res1[0x20 - 0xc];
  322. u16 typeorlen;
  323. u8 res2[0x1];
  324. u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
  325. u32 rxrmonbaseptr; /* Rx RMON statistics base */
  326. u8 res3[0x30 - 0x28];
  327. u32 intcoalescingptr; /* Interrupt coalescing table pointer */
  328. u8 res4[0x36 - 0x34];
  329. u8 rstate;
  330. u8 res5[0x46 - 0x37];
  331. u16 mrblr; /* max receive buffer length reg. */
  332. u32 rbdqptr; /* RxBD parameter table description */
  333. u16 mflr; /* max frame length reg. */
  334. u16 minflr; /* min frame length reg. */
  335. u16 maxd1; /* max dma1 length reg. */
  336. u16 maxd2; /* max dma2 length reg. */
  337. u32 ecamptr; /* external CAM address */
  338. u32 l2qt; /* VLAN priority mapping table. */
  339. u32 l3qt[0x8]; /* IP priority mapping table. */
  340. u16 vlantype; /* vlan type */
  341. u16 vlantci; /* default vlan tci */
  342. u8 addressfiltering[64];/* address filtering data structure */
  343. u32 exf_global_param; /* extended filtering global parameters */
  344. u8 res6[0x100 - 0xc4]; /* Initialize to zero */
  345. } __packed;
  346. #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
  347. /****** UEC common ******/
  348. /* UCC statistics - hardware counters */
  349. struct uec_hardware_statistics {
  350. u32 tx64;
  351. u32 tx127;
  352. u32 tx255;
  353. u32 rx64;
  354. u32 rx127;
  355. u32 rx255;
  356. u32 txok;
  357. u16 txcf;
  358. u32 tmca;
  359. u32 tbca;
  360. u32 rxfok;
  361. u32 rxbok;
  362. u32 rbyt;
  363. u32 rmca;
  364. u32 rbca;
  365. } __packed;
  366. /* InitEnet command parameter */
  367. struct uec_init_cmd_pram {
  368. u8 resinit0;
  369. u8 resinit1;
  370. u8 resinit2;
  371. u8 resinit3;
  372. u16 resinit4;
  373. u8 res1[0x1];
  374. u8 largestexternallookupkeysize;
  375. u32 rgftgfrxglobal;
  376. u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
  377. u8 res2[0x38 - 0x30];
  378. u32 txglobal; /* tx global */
  379. u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
  380. u8 res3[0x1];
  381. } __packed;
  382. #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
  383. #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
  384. #define ENET_INIT_PARAM_RISC_MASK 0x0000003f
  385. #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
  386. #define ENET_INIT_PARAM_SNUM_MASK 0xff000000
  387. #define ENET_INIT_PARAM_SNUM_SHIFT 24
  388. #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
  389. #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
  390. #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
  391. #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
  392. #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
  393. /* structure representing 82xx Address Filtering Enet Address in PRAM */
  394. struct uec_82xx_enet_addr {
  395. u8 res1[0x2];
  396. u16 h; /* address (MSB) */
  397. u16 m; /* address */
  398. u16 l; /* address (LSB) */
  399. } __packed;
  400. /* structure representing 82xx Address Filtering PRAM */
  401. struct uec_82xx_add_filtering_pram {
  402. u32 iaddr_h; /* individual address filter, high */
  403. u32 iaddr_l; /* individual address filter, low */
  404. u32 gaddr_h; /* group address filter, high */
  405. u32 gaddr_l; /* group address filter, low */
  406. struct uec_82xx_enet_addr taddr;
  407. struct uec_82xx_enet_addr paddr[4];
  408. u8 res0[0x40 - 0x38];
  409. } __packed;
  410. /* Buffer Descriptor */
  411. struct buffer_descriptor {
  412. u16 status;
  413. u16 len;
  414. u32 data;
  415. } __packed;
  416. #define SIZEOFBD sizeof(struct buffer_descriptor)
  417. /* Common BD flags */
  418. #define BD_WRAP 0x2000
  419. #define BD_INT 0x1000
  420. #define BD_LAST 0x0800
  421. #define BD_CLEAN 0x3000
  422. /* TxBD status flags */
  423. #define TX_BD_READY 0x8000
  424. #define TX_BD_PADCRC 0x4000
  425. #define TX_BD_WRAP BD_WRAP
  426. #define TX_BD_INT BD_INT
  427. #define TX_BD_LAST BD_LAST
  428. #define TX_BD_TXCRC 0x0400
  429. #define TX_BD_DEF 0x0200
  430. #define TX_BD_PP 0x0100
  431. #define TX_BD_LC 0x0080
  432. #define TX_BD_RL 0x0040
  433. #define TX_BD_RC 0x003C
  434. #define TX_BD_UNDERRUN 0x0002
  435. #define TX_BD_TRUNC 0x0001
  436. #define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC)
  437. /* RxBD status flags */
  438. #define RX_BD_EMPTY 0x8000
  439. #define RX_BD_OWNER 0x4000
  440. #define RX_BD_WRAP BD_WRAP
  441. #define RX_BD_INT BD_INT
  442. #define RX_BD_LAST BD_LAST
  443. #define RX_BD_FIRST 0x0400
  444. #define RX_BD_CMR 0x0200
  445. #define RX_BD_MISS 0x0100
  446. #define RX_BD_BCAST 0x0080
  447. #define RX_BD_MCAST 0x0040
  448. #define RX_BD_LG 0x0020
  449. #define RX_BD_NO 0x0010
  450. #define RX_BD_SHORT 0x0008
  451. #define RX_BD_CRCERR 0x0004
  452. #define RX_BD_OVERRUN 0x0002
  453. #define RX_BD_IPCH 0x0001
  454. #define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
  455. RX_BD_CRCERR | RX_BD_OVERRUN)
  456. /* BD access macros */
  457. #define BD_STATUS(_bd) (in_be16(&((_bd)->status)))
  458. #define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v))
  459. #define BD_LENGTH(_bd) (in_be16(&((_bd)->len)))
  460. #define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v))
  461. #define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0))
  462. #define BD_DATA(_bd) ((u8 *)(((_bd)->data)))
  463. #define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data))
  464. #define BD_ADVANCE(_bd, _status, _base) \
  465. (((_status) & BD_WRAP) ? (_bd) = \
  466. ((struct buffer_descriptor *)(_base)) : ++(_bd))
  467. /* Rx Prefetched BDs */
  468. struct uec_rx_pref_bds {
  469. struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
  470. } __packed;
  471. /* Alignments */
  472. #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
  473. #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
  474. #define UEC_THREAD_RX_PRAM_ALIGNMENT 128
  475. #define UEC_THREAD_TX_PRAM_ALIGNMENT 64
  476. #define UEC_THREAD_DATA_ALIGNMENT 256
  477. #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
  478. #define UEC_SCHEDULER_ALIGNMENT 4
  479. #define UEC_TX_STATISTICS_ALIGNMENT 4
  480. #define UEC_RX_STATISTICS_ALIGNMENT 4
  481. #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
  482. #define UEC_RX_BD_QUEUES_ALIGNMENT 8
  483. #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
  484. #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
  485. #define UEC_RX_BD_RING_ALIGNMENT 32
  486. #define UEC_TX_BD_RING_ALIGNMENT 32
  487. #define UEC_MRBLR_ALIGNMENT 128
  488. #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
  489. #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
  490. #define UEC_RX_DATA_BUF_ALIGNMENT 64
  491. #define UEC_VLAN_PRIORITY_MAX 8
  492. #define UEC_IP_PRIORITY_MAX 64
  493. #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
  494. #define UEC_RX_BD_RING_SIZE_MIN 8
  495. #define UEC_TX_BD_RING_SIZE_MIN 2
  496. /* TBI / MII Set Register */
  497. enum enet_tbi_mii_reg {
  498. ENET_TBI_MII_CR = 0x00,
  499. ENET_TBI_MII_SR = 0x01,
  500. ENET_TBI_MII_ANA = 0x04,
  501. ENET_TBI_MII_ANLPBPA = 0x05,
  502. ENET_TBI_MII_ANEX = 0x06,
  503. ENET_TBI_MII_ANNPT = 0x07,
  504. ENET_TBI_MII_ANLPANP = 0x08,
  505. ENET_TBI_MII_EXST = 0x0F,
  506. ENET_TBI_MII_JD = 0x10,
  507. ENET_TBI_MII_TBICON = 0x11
  508. };
  509. /* TBI MDIO register bit fields*/
  510. #define TBICON_CLK_SELECT 0x0020
  511. #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  512. #define TBIANA_SYMMETRIC_PAUSE 0x0080
  513. #define TBIANA_HALF_DUPLEX 0x0040
  514. #define TBIANA_FULL_DUPLEX 0x0020
  515. #define TBICR_PHY_RESET 0x8000
  516. #define TBICR_ANEG_ENABLE 0x1000
  517. #define TBICR_RESTART_ANEG 0x0200
  518. #define TBICR_FULL_DUPLEX 0x0100
  519. #define TBICR_SPEED1_SET 0x0040
  520. #define TBIANA_SETTINGS ( \
  521. TBIANA_ASYMMETRIC_PAUSE \
  522. | TBIANA_SYMMETRIC_PAUSE \
  523. | TBIANA_FULL_DUPLEX \
  524. )
  525. #define TBICR_SETTINGS ( \
  526. TBICR_PHY_RESET \
  527. | TBICR_ANEG_ENABLE \
  528. | TBICR_FULL_DUPLEX \
  529. | TBICR_SPEED1_SET \
  530. )
  531. /* UEC number of threads */
  532. enum uec_num_of_threads {
  533. UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
  534. UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
  535. UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
  536. UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
  537. UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
  538. };
  539. /* UEC initialization info struct */
  540. #define STD_UEC_INFO(num) \
  541. { \
  542. .uf_info = { \
  543. .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
  544. .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
  545. .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
  546. .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
  547. }, \
  548. .num_threads_tx = UEC_NUM_OF_THREADS_1, \
  549. .num_threads_rx = UEC_NUM_OF_THREADS_1, \
  550. .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
  551. .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
  552. .tx_bd_ring_len = 16, \
  553. .rx_bd_ring_len = 16, \
  554. .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
  555. .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
  556. .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
  557. }
  558. struct uec_inf {
  559. struct ucc_fast_inf uf_info;
  560. enum uec_num_of_threads num_threads_tx;
  561. enum uec_num_of_threads num_threads_rx;
  562. unsigned int risc_tx;
  563. unsigned int risc_rx;
  564. u16 rx_bd_ring_len;
  565. u16 tx_bd_ring_len;
  566. u8 phy_address;
  567. phy_interface_t enet_interface_type;
  568. int speed;
  569. };
  570. /* UEC driver initialized info */
  571. #define MAX_RXBUF_LEN 1536
  572. #define MAX_FRAME_LEN 1518
  573. #define MIN_FRAME_LEN 64
  574. #define MAX_DMA1_LEN 1520
  575. #define MAX_DMA2_LEN 1520
  576. /* UEC driver private struct */
  577. struct uec_priv {
  578. struct uec_inf *uec_info;
  579. struct ucc_fast_priv *uccf;
  580. struct eth_device *dev;
  581. uec_t *uec_regs;
  582. /* enet init command parameter */
  583. struct uec_init_cmd_pram *p_init_enet_param;
  584. u32 init_enet_param_offset;
  585. /* Rx and Tx parameter */
  586. struct uec_rx_global_pram *p_rx_glbl_pram;
  587. u32 rx_glbl_pram_offset;
  588. struct uec_tx_global_pram *p_tx_glbl_pram;
  589. u32 tx_glbl_pram_offset;
  590. struct uec_send_queue_mem_region *p_send_q_mem_reg;
  591. u32 send_q_mem_reg_offset;
  592. struct uec_thread_data_tx *p_thread_data_tx;
  593. u32 thread_dat_tx_offset;
  594. struct uec_thread_data_rx *p_thread_data_rx;
  595. u32 thread_dat_rx_offset;
  596. struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl;
  597. u32 rx_bd_qs_tbl_offset;
  598. /* BDs specific */
  599. u8 *p_tx_bd_ring;
  600. u32 tx_bd_ring_offset;
  601. u8 *p_rx_bd_ring;
  602. u32 rx_bd_ring_offset;
  603. u8 *p_rx_buf;
  604. u32 rx_buf_offset;
  605. struct buffer_descriptor *tx_bd;
  606. struct buffer_descriptor *rx_bd;
  607. /* Status */
  608. int mac_tx_enabled;
  609. int mac_rx_enabled;
  610. int grace_stopped_tx;
  611. int grace_stopped_rx;
  612. int the_first_run;
  613. #if !defined(COFIG_DM)
  614. /* PHY specific */
  615. struct uec_mii_info *mii_info;
  616. int oldspeed;
  617. int oldduplex;
  618. int oldlink;
  619. #endif
  620. };
  621. int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
  622. int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
  623. int uec_standard_init(struct bd_info *bis);
  624. #endif /* __UEC_H__ */