uccf.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <linux/errno.h>
  11. #include <asm/io.h>
  12. #include <linux/immap_qe.h>
  13. #include "uccf.h"
  14. #include <fsl_qe.h>
  15. void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
  16. {
  17. out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
  18. }
  19. u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
  20. {
  21. switch (ucc_num) {
  22. case 0:
  23. return QE_CR_SUBBLOCK_UCCFAST1;
  24. case 1:
  25. return QE_CR_SUBBLOCK_UCCFAST2;
  26. case 2:
  27. return QE_CR_SUBBLOCK_UCCFAST3;
  28. case 3:
  29. return QE_CR_SUBBLOCK_UCCFAST4;
  30. case 4:
  31. return QE_CR_SUBBLOCK_UCCFAST5;
  32. case 5:
  33. return QE_CR_SUBBLOCK_UCCFAST6;
  34. case 6:
  35. return QE_CR_SUBBLOCK_UCCFAST7;
  36. case 7:
  37. return QE_CR_SUBBLOCK_UCCFAST8;
  38. default:
  39. return QE_CR_SUBBLOCK_INVALID;
  40. }
  41. }
  42. static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
  43. u8 *reg_num, u8 *shift)
  44. {
  45. switch (ucc_num) {
  46. case 0: /* UCC1 */
  47. *p_cmxucr = &qe_immr->qmx.cmxucr1;
  48. *reg_num = 1;
  49. *shift = 16;
  50. break;
  51. case 2: /* UCC3 */
  52. *p_cmxucr = &qe_immr->qmx.cmxucr1;
  53. *reg_num = 1;
  54. *shift = 0;
  55. break;
  56. case 4: /* UCC5 */
  57. *p_cmxucr = &qe_immr->qmx.cmxucr2;
  58. *reg_num = 2;
  59. *shift = 16;
  60. break;
  61. case 6: /* UCC7 */
  62. *p_cmxucr = &qe_immr->qmx.cmxucr2;
  63. *reg_num = 2;
  64. *shift = 0;
  65. break;
  66. case 1: /* UCC2 */
  67. *p_cmxucr = &qe_immr->qmx.cmxucr3;
  68. *reg_num = 3;
  69. *shift = 16;
  70. break;
  71. case 3: /* UCC4 */
  72. *p_cmxucr = &qe_immr->qmx.cmxucr3;
  73. *reg_num = 3;
  74. *shift = 0;
  75. break;
  76. case 5: /* UCC6 */
  77. *p_cmxucr = &qe_immr->qmx.cmxucr4;
  78. *reg_num = 4;
  79. *shift = 16;
  80. break;
  81. case 7: /* UCC8 */
  82. *p_cmxucr = &qe_immr->qmx.cmxucr4;
  83. *reg_num = 4;
  84. *shift = 0;
  85. break;
  86. default:
  87. break;
  88. }
  89. }
  90. static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
  91. {
  92. u32 *p_cmxucr = NULL;
  93. u8 reg_num = 0;
  94. u8 shift = 0;
  95. u32 clk_bits;
  96. u32 clk_mask;
  97. int source = -1;
  98. /* check if the UCC number is in range. */
  99. if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
  100. return -EINVAL;
  101. if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
  102. printf("%s: bad comm mode type passed\n", __func__);
  103. return -EINVAL;
  104. }
  105. ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
  106. switch (reg_num) {
  107. case 1:
  108. switch (clock) {
  109. case QE_BRG1:
  110. source = 1;
  111. break;
  112. case QE_BRG2:
  113. source = 2;
  114. break;
  115. case QE_BRG7:
  116. source = 3;
  117. break;
  118. case QE_BRG8:
  119. source = 4;
  120. break;
  121. case QE_CLK9:
  122. source = 5;
  123. break;
  124. case QE_CLK10:
  125. source = 6;
  126. break;
  127. case QE_CLK11:
  128. source = 7;
  129. break;
  130. case QE_CLK12:
  131. source = 8;
  132. break;
  133. case QE_CLK15:
  134. source = 9;
  135. break;
  136. case QE_CLK16:
  137. source = 10;
  138. break;
  139. default:
  140. source = -1;
  141. break;
  142. }
  143. break;
  144. case 2:
  145. switch (clock) {
  146. case QE_BRG5:
  147. source = 1;
  148. break;
  149. case QE_BRG6:
  150. source = 2;
  151. break;
  152. case QE_BRG7:
  153. source = 3;
  154. break;
  155. case QE_BRG8:
  156. source = 4;
  157. break;
  158. case QE_CLK13:
  159. source = 5;
  160. break;
  161. case QE_CLK14:
  162. source = 6;
  163. break;
  164. case QE_CLK19:
  165. source = 7;
  166. break;
  167. case QE_CLK20:
  168. source = 8;
  169. break;
  170. case QE_CLK15:
  171. source = 9;
  172. break;
  173. case QE_CLK16:
  174. source = 10;
  175. break;
  176. default:
  177. source = -1;
  178. break;
  179. }
  180. break;
  181. case 3:
  182. switch (clock) {
  183. case QE_BRG9:
  184. source = 1;
  185. break;
  186. case QE_BRG10:
  187. source = 2;
  188. break;
  189. case QE_BRG15:
  190. source = 3;
  191. break;
  192. case QE_BRG16:
  193. source = 4;
  194. break;
  195. case QE_CLK3:
  196. source = 5;
  197. break;
  198. case QE_CLK4:
  199. source = 6;
  200. break;
  201. case QE_CLK17:
  202. source = 7;
  203. break;
  204. case QE_CLK18:
  205. source = 8;
  206. break;
  207. case QE_CLK7:
  208. source = 9;
  209. break;
  210. case QE_CLK8:
  211. source = 10;
  212. break;
  213. case QE_CLK16:
  214. source = 11;
  215. break;
  216. default:
  217. source = -1;
  218. break;
  219. }
  220. break;
  221. case 4:
  222. switch (clock) {
  223. case QE_BRG13:
  224. source = 1;
  225. break;
  226. case QE_BRG14:
  227. source = 2;
  228. break;
  229. case QE_BRG15:
  230. source = 3;
  231. break;
  232. case QE_BRG16:
  233. source = 4;
  234. break;
  235. case QE_CLK5:
  236. source = 5;
  237. break;
  238. case QE_CLK6:
  239. source = 6;
  240. break;
  241. case QE_CLK21:
  242. source = 7;
  243. break;
  244. case QE_CLK22:
  245. source = 8;
  246. break;
  247. case QE_CLK7:
  248. source = 9;
  249. break;
  250. case QE_CLK8:
  251. source = 10;
  252. break;
  253. case QE_CLK16:
  254. source = 11;
  255. break;
  256. default:
  257. source = -1;
  258. break;
  259. }
  260. break;
  261. default:
  262. source = -1;
  263. break;
  264. }
  265. if (source == -1) {
  266. printf("%s: Bad combination of clock and UCC\n", __func__);
  267. return -ENOENT;
  268. }
  269. clk_bits = (u32)source;
  270. clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
  271. if (mode == COMM_DIR_RX) {
  272. clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
  273. clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
  274. }
  275. clk_bits <<= shift;
  276. clk_mask <<= shift;
  277. out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
  278. return 0;
  279. }
  280. static uint ucc_get_reg_baseaddr(int ucc_num)
  281. {
  282. uint base = 0;
  283. /* check if the UCC number is in range */
  284. if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
  285. printf("%s: the UCC num not in ranges\n", __func__);
  286. return 0;
  287. }
  288. switch (ucc_num) {
  289. case 0:
  290. base = 0x00002000;
  291. break;
  292. case 1:
  293. base = 0x00003000;
  294. break;
  295. case 2:
  296. base = 0x00002200;
  297. break;
  298. case 3:
  299. base = 0x00003200;
  300. break;
  301. case 4:
  302. base = 0x00002400;
  303. break;
  304. case 5:
  305. base = 0x00003400;
  306. break;
  307. case 6:
  308. base = 0x00002600;
  309. break;
  310. case 7:
  311. base = 0x00003600;
  312. break;
  313. default:
  314. break;
  315. }
  316. base = (uint)qe_immr + base;
  317. return base;
  318. }
  319. void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
  320. {
  321. ucc_fast_t *uf_regs;
  322. u32 gumr;
  323. uf_regs = uccf->uf_regs;
  324. /* Enable reception and/or transmission on this UCC. */
  325. gumr = in_be32(&uf_regs->gumr);
  326. if (mode & COMM_DIR_TX) {
  327. gumr |= UCC_FAST_GUMR_ENT;
  328. uccf->enabled_tx = 1;
  329. }
  330. if (mode & COMM_DIR_RX) {
  331. gumr |= UCC_FAST_GUMR_ENR;
  332. uccf->enabled_rx = 1;
  333. }
  334. out_be32(&uf_regs->gumr, gumr);
  335. }
  336. void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
  337. {
  338. ucc_fast_t *uf_regs;
  339. u32 gumr;
  340. uf_regs = uccf->uf_regs;
  341. /* Disable reception and/or transmission on this UCC. */
  342. gumr = in_be32(&uf_regs->gumr);
  343. if (mode & COMM_DIR_TX) {
  344. gumr &= ~UCC_FAST_GUMR_ENT;
  345. uccf->enabled_tx = 0;
  346. }
  347. if (mode & COMM_DIR_RX) {
  348. gumr &= ~UCC_FAST_GUMR_ENR;
  349. uccf->enabled_rx = 0;
  350. }
  351. out_be32(&uf_regs->gumr, gumr);
  352. }
  353. int ucc_fast_init(struct ucc_fast_inf *uf_info,
  354. struct ucc_fast_priv **uccf_ret)
  355. {
  356. struct ucc_fast_priv *uccf;
  357. ucc_fast_t *uf_regs;
  358. if (!uf_info)
  359. return -EINVAL;
  360. if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
  361. printf("%s: Illagal UCC number!\n", __func__);
  362. return -EINVAL;
  363. }
  364. uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
  365. if (!uccf) {
  366. printf("%s: No memory for UCC fast data structure!\n",
  367. __func__);
  368. return -ENOMEM;
  369. }
  370. memset(uccf, 0, sizeof(struct ucc_fast_priv));
  371. /* Save fast UCC structure */
  372. uccf->uf_info = uf_info;
  373. uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
  374. if (!uccf->uf_regs) {
  375. printf("%s: No memory map for UCC fast controller!\n",
  376. __func__);
  377. return -ENOMEM;
  378. }
  379. uccf->enabled_tx = 0;
  380. uccf->enabled_rx = 0;
  381. uf_regs = uccf->uf_regs;
  382. uccf->p_ucce = (u32 *)&uf_regs->ucce;
  383. uccf->p_uccm = (u32 *)&uf_regs->uccm;
  384. /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
  385. out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
  386. | UCC_GUEMR_MODE_FAST_TX);
  387. /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
  388. out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
  389. /* Set the Giga ethernet VFIFO stuff */
  390. if (uf_info->eth_type == GIGA_ETH) {
  391. /* Allocate memory for Tx Virtual Fifo */
  392. uccf->ucc_fast_tx_virtual_fifo_base_offset =
  393. qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
  394. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  395. /* Allocate memory for Rx Virtual Fifo */
  396. uccf->ucc_fast_rx_virtual_fifo_base_offset =
  397. qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
  398. UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
  399. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  400. /* utfb, urfb are offsets from MURAM base */
  401. out_be32(&uf_regs->utfb,
  402. uccf->ucc_fast_tx_virtual_fifo_base_offset);
  403. out_be32(&uf_regs->urfb,
  404. uccf->ucc_fast_rx_virtual_fifo_base_offset);
  405. /* Set Virtual Fifo registers */
  406. out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
  407. out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
  408. out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
  409. out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
  410. out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
  411. out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
  412. }
  413. /* Set the Fast ethernet VFIFO stuff */
  414. if (uf_info->eth_type == FAST_ETH) {
  415. /* Allocate memory for Tx Virtual Fifo */
  416. uccf->ucc_fast_tx_virtual_fifo_base_offset =
  417. qe_muram_alloc(UCC_GETH_UTFS_INIT,
  418. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  419. /* Allocate memory for Rx Virtual Fifo */
  420. uccf->ucc_fast_rx_virtual_fifo_base_offset =
  421. qe_muram_alloc(UCC_GETH_URFS_INIT +
  422. UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
  423. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  424. /* utfb, urfb are offsets from MURAM base */
  425. out_be32(&uf_regs->utfb,
  426. uccf->ucc_fast_tx_virtual_fifo_base_offset);
  427. out_be32(&uf_regs->urfb,
  428. uccf->ucc_fast_rx_virtual_fifo_base_offset);
  429. /* Set Virtual Fifo registers */
  430. out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
  431. out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
  432. out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
  433. out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
  434. out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
  435. out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
  436. }
  437. /* Rx clock routing */
  438. if (uf_info->rx_clock != QE_CLK_NONE) {
  439. if (ucc_set_clk_src(uf_info->ucc_num,
  440. uf_info->rx_clock, COMM_DIR_RX)) {
  441. printf("%s: Illegal value for parameter 'RxClock'.\n",
  442. __func__);
  443. return -EINVAL;
  444. }
  445. }
  446. /* Tx clock routing */
  447. if (uf_info->tx_clock != QE_CLK_NONE) {
  448. if (ucc_set_clk_src(uf_info->ucc_num,
  449. uf_info->tx_clock, COMM_DIR_TX)) {
  450. printf("%s: Illegal value for parameter 'TxClock'.\n",
  451. __func__);
  452. return -EINVAL;
  453. }
  454. }
  455. /* Clear interrupt mask register to disable all of interrupts */
  456. out_be32(&uf_regs->uccm, 0x0);
  457. /* Writing '1' to clear all of envents */
  458. out_be32(&uf_regs->ucce, 0xffffffff);
  459. *uccf_ret = uccf;
  460. return 0;
  461. }