luan.c 10 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * John Otken, jotken@softadvances.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <ppc4xx.h>
  26. #include <asm/processor.h>
  27. #include <spd_sdram.h>
  28. #include "epld.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  31. /*************************************************************************
  32. * int board_early_init_f()
  33. *
  34. ************************************************************************/
  35. int board_early_init_f(void)
  36. {
  37. u32 mfr;
  38. mtebc( pb0ap, 0x03800000 ); /* set chip selects */
  39. mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
  40. mtebc( pb1ap, 0x03800000 );
  41. mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
  42. mtebc( pb2ap, 0x03800000 );
  43. mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
  44. mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
  45. mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
  46. mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
  47. mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
  48. mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
  49. mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
  50. mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
  51. mtdcr( uic1sr, 0xffffffff );
  52. mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
  53. mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
  54. mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
  55. mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
  56. mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
  57. mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
  58. mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
  59. mtdcr( uic0sr, 0xffffffff );
  60. mfsdr(sdr_mfr, mfr);
  61. mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
  62. mtsdr(sdr_mfr, mfr);
  63. return 0;
  64. }
  65. /*************************************************************************
  66. * int misc_init_r()
  67. *
  68. ************************************************************************/
  69. int misc_init_r(void)
  70. {
  71. volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
  72. /* set modes of operation */
  73. x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
  74. EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
  75. /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
  76. x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
  77. /* put Ethernet+PHY in reset */
  78. x->ethuart &= ~EPLD2_RESET_ETH_N;
  79. udelay(10000);
  80. /* take Ethernet+PHY out of reset */
  81. x->ethuart |= EPLD2_RESET_ETH_N;
  82. return 0;
  83. }
  84. /*************************************************************************
  85. * int checkboard()
  86. *
  87. ************************************************************************/
  88. int checkboard(void)
  89. {
  90. char *s = getenv("serial#");
  91. printf("Board: Luan - AMCC PPC440SP Evaluation Board");
  92. if (s != NULL) {
  93. puts(", serial# ");
  94. puts(s);
  95. }
  96. putc('\n');
  97. return 0;
  98. }
  99. /*
  100. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  101. * board specific values.
  102. */
  103. u32 ddr_clktr(u32 default_val) {
  104. return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
  105. }
  106. /*************************************************************************
  107. * pci_pre_init
  108. *
  109. * This routine is called just prior to registering the hose and gives
  110. * the board the opportunity to check things. Returning a value of zero
  111. * indicates that things are bad & PCI initialization should be aborted.
  112. *
  113. * Different boards may wish to customize the pci controller structure
  114. * (add regions, override default access routines, etc) or perform
  115. * certain pre-initialization actions.
  116. *
  117. ************************************************************************/
  118. #if defined(CONFIG_PCI)
  119. int pci_pre_init( struct pci_controller *hose )
  120. {
  121. unsigned long strap;
  122. /*--------------------------------------------------------------------------+
  123. * The luan board is always configured as the host & requires the
  124. * PCI arbiter to be enabled.
  125. *--------------------------------------------------------------------------*/
  126. mfsdr(sdr_sdstp1, strap);
  127. if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
  128. printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
  129. return 0;
  130. }
  131. return 1;
  132. }
  133. #endif /* defined(CONFIG_PCI) */
  134. /*************************************************************************
  135. * pci_target_init
  136. *
  137. * The bootstrap configuration provides default settings for the pci
  138. * inbound map (PIM). But the bootstrap config choices are limited and
  139. * may not be sufficient for a given board.
  140. *
  141. ************************************************************************/
  142. #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
  143. void pci_target_init(struct pci_controller *hose)
  144. {
  145. /*--------------------------------------------------------------------------+
  146. * Disable everything
  147. *--------------------------------------------------------------------------*/
  148. out32r( PCIX0_PIM0SA, 0 ); /* disable */
  149. out32r( PCIX0_PIM1SA, 0 ); /* disable */
  150. out32r( PCIX0_PIM2SA, 0 ); /* disable */
  151. out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
  152. /*--------------------------------------------------------------------------+
  153. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
  154. * options to not support sizes such as 128/256 MB.
  155. *--------------------------------------------------------------------------*/
  156. out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
  157. out32r( PCIX0_PIM0LAH, 0 );
  158. out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
  159. out32r( PCIX0_BAR0, 0 );
  160. /*--------------------------------------------------------------------------+
  161. * Program the board's subsystem id/vendor id
  162. *--------------------------------------------------------------------------*/
  163. out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
  164. out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
  165. out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
  166. }
  167. #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
  168. /*************************************************************************
  169. * is_pci_host
  170. *
  171. * This routine is called to determine if a pci scan should be
  172. * performed. With various hardware environments (especially cPCI and
  173. * PPMC) it's insufficient to depend on the state of the arbiter enable
  174. * bit in the strap register, or generic host/adapter assumptions.
  175. *
  176. * Rather than hard-code a bad assumption in the general 440 code, the
  177. * 440 pci code requires the board to decide at runtime.
  178. *
  179. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  180. *
  181. *
  182. ************************************************************************/
  183. #if defined(CONFIG_PCI)
  184. int is_pci_host(struct pci_controller *hose)
  185. {
  186. return 1;
  187. }
  188. #endif /* defined(CONFIG_PCI) */
  189. /*************************************************************************
  190. * hw_watchdog_reset
  191. *
  192. * This routine is called to reset (keep alive) the watchdog timer
  193. *
  194. ************************************************************************/
  195. #if defined(CONFIG_HW_WATCHDOG)
  196. void hw_watchdog_reset(void)
  197. {
  198. }
  199. #endif
  200. /*************************************************************************
  201. * int on_off()
  202. *
  203. ************************************************************************/
  204. static int on_off( const char *s )
  205. {
  206. if (strcmp(s, "on") == 0) {
  207. return 1;
  208. } else if (strcmp(s, "off") == 0) {
  209. return 0;
  210. }
  211. return -1;
  212. }
  213. /*************************************************************************
  214. * void l2cache_disable()
  215. *
  216. ************************************************************************/
  217. static void l2cache_disable(void)
  218. {
  219. mtdcr( l2_cache_cfg, 0 );
  220. }
  221. /*************************************************************************
  222. * void l2cache_enable()
  223. *
  224. ************************************************************************/
  225. static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
  226. {
  227. mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
  228. mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
  229. mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
  230. while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
  231. mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
  232. mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
  233. mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
  234. mtdcr( l2_cache_snp1, 0 );
  235. __asm__ volatile ("sync"); /* msync */
  236. mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
  237. __asm__ volatile ("sync");
  238. }
  239. /*************************************************************************
  240. * int l2cache_status()
  241. *
  242. ************************************************************************/
  243. static int l2cache_status(void)
  244. {
  245. return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
  246. }
  247. /*************************************************************************
  248. * int do_l2cache()
  249. *
  250. ************************************************************************/
  251. int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
  252. {
  253. switch (argc) {
  254. case 2: /* on / off */
  255. switch (on_off(argv[1])) {
  256. case 0: l2cache_disable();
  257. break;
  258. case 1: l2cache_enable();
  259. break;
  260. }
  261. /* FALL TROUGH */
  262. case 1: /* get status */
  263. printf ("L2 Cache is %s\n",
  264. l2cache_status() ? "ON" : "OFF");
  265. return 0;
  266. default:
  267. printf ("Usage:\n%s\n", cmdtp->usage);
  268. return 1;
  269. }
  270. return 0;
  271. }
  272. U_BOOT_CMD(
  273. l2cache, 2, 1, do_l2cache,
  274. "l2cache - enable or disable L2 cache\n",
  275. "[on, off]\n"
  276. " - enable or disable L2 cache\n"
  277. );