init.S 2.6 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <ppc_asm.tmpl>
  26. #include <config.h>
  27. #include <asm-ppc/mmu.h>
  28. /**************************************************************************
  29. * TLB TABLE
  30. *
  31. * This table is used by the cpu boot code to setup the initial tlb
  32. * entries. Rather than make broad assumptions in the cpu source tree,
  33. * this table lets each board set things up however they like.
  34. *
  35. * Pointer to the table is returned in r1
  36. *
  37. *************************************************************************/
  38. .section .bootpg,"ax"
  39. .globl tlbtab
  40. tlbtab:
  41. tlbtab_start
  42. /*
  43. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  44. * speed up boot process. It is patched after relocation to enable SA_I
  45. */
  46. tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
  47. tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  48. tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  49. tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  50. tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  51. tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
  52. /*
  53. * TLB entries for SDRAM are not needed on this platform.
  54. * They are dynamically generated in the SPD DDR(2) detection
  55. * routine.
  56. */
  57. /* internal ram (l2 cache) */
  58. tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
  59. /* peripherals at f0000000 */
  60. tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
  61. /* PCI */
  62. tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
  63. tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
  64. tlbtab_end