kilauea.c 15 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <ppc4xx.h>
  25. #include <ppc405.h>
  26. #include <libfdt.h>
  27. #include <fdt_support.h>
  28. #include <asm/processor.h>
  29. #include <asm/io.h>
  30. #if defined(CONFIG_PCI)
  31. #include <pci.h>
  32. #include <asm/4xx_pcie.h>
  33. #endif
  34. DECLARE_GLOBAL_DATA_PTR;
  35. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  36. /*
  37. * Board early initialization function
  38. */
  39. int board_early_init_f (void)
  40. {
  41. u32 val;
  42. /*--------------------------------------------------------------------+
  43. | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
  44. +--------------------------------------------------------------------+
  45. +---------------------------------------------------------------------+
  46. |Interrupt| Source | Pol. | Sensi.| Crit. |
  47. +---------+-----------------------------------+-------+-------+-------+
  48. | IRQ 00 | UART0 | High | Level | Non |
  49. | IRQ 01 | UART1 | High | Level | Non |
  50. | IRQ 02 | IIC0 | High | Level | Non |
  51. | IRQ 03 | TBD | High | Level | Non |
  52. | IRQ 04 | TBD | High | Level | Non |
  53. | IRQ 05 | EBM | High | Level | Non |
  54. | IRQ 06 | BGI | High | Level | Non |
  55. | IRQ 07 | IIC1 | Rising| Edge | Non |
  56. | IRQ 08 | SPI | High | Lvl/ed| Non |
  57. | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
  58. | IRQ 10 | MAL TX EOB | High | Level | Non |
  59. | IRQ 11 | MAL RX EOB | High | Level | Non |
  60. | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
  61. | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
  62. | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
  63. | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
  64. | IRQ 16 | PCIE0 AL | high | Level | Non |
  65. | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
  66. | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
  67. | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
  68. | IRQ 20 | PCIE0 TCR | High | Level | Non |
  69. | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
  70. | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
  71. | IRQ 23 | Security EIP-94 | High | Level | Non |
  72. | IRQ 24 | EMAC0 interrupt | High | Level | Non |
  73. | IRQ 25 | EMAC1 interrupt | High | Level | Non |
  74. | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
  75. | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
  76. | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
  77. | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
  78. | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
  79. | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
  80. |----------------------------------------------------------------------
  81. | IRQ 32 | MAL Serr | High | Level | Non |
  82. | IRQ 33 | MAL Txde | High | Level | Non |
  83. | IRQ 34 | MAL Rxde | High | Level | Non |
  84. | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
  85. | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
  86. | IRQ 37 | EBC | High |Lvl Edg| Non |
  87. | IRQ 38 | NDFC | High | Level | Non |
  88. | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
  89. | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
  90. | IRQ 41 | PCIE1 AL | high | Level | Non |
  91. | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
  92. | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
  93. | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
  94. | IRQ 45 | PCIE1 TCR | High | Level | Non |
  95. | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
  96. | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
  97. | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
  98. | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
  99. | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
  100. | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
  101. | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
  102. | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
  103. | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
  104. | IRQ 55 | Serial ROM | High | Level | Non |
  105. | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
  106. | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
  107. | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
  108. | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
  109. | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
  110. | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
  111. | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
  112. |----------------------------------------------------------------------
  113. | IRQ 64 | PE0 AL | High | Level | Non |
  114. | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
  115. | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
  116. | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
  117. | IRQ 68 | PE0 TCR | High | Level | Non |
  118. | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
  119. | IRQ 70 | PE0 DCR Error | High | Level | Non |
  120. | IRQ 71 | Reserved | N/A | N/A | Non |
  121. | IRQ 72 | PE1 AL | High | Level | Non |
  122. | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
  123. | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
  124. | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
  125. | IRQ 76 | PE1 TCR | High | Level | Non |
  126. | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
  127. | IRQ 78 | PE1 DCR Error | High | Level | Non |
  128. | IRQ 79 | Reserved | N/A | N/A | Non |
  129. | IRQ 80 | PE2 AL | High | Level | Non |
  130. | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
  131. | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
  132. | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
  133. | IRQ 84 | PE2 TCR | High | Level | Non |
  134. | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
  135. | IRQ 86 | PE2 DCR Error | High | Level | Non |
  136. | IRQ 87 | Reserved | N/A | N/A | Non |
  137. | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
  138. | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
  139. | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
  140. | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
  141. | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
  142. | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
  143. | IRQ 94 | Reserved | N/A | N/A | Non |
  144. | IRQ 95 | Reserved | N/A | N/A | Non |
  145. |---------------------------------------------------------------------
  146. +---------+-----------------------------------+-------+-------+------*/
  147. /*--------------------------------------------------------------------+
  148. | Initialise UIC registers. Clear all interrupts. Disable all
  149. | interrupts.
  150. | Set critical interrupt values. Set interrupt polarities. Set
  151. | interrupt trigger levels. Make bit 0 High priority. Clear all
  152. | interrupts again.
  153. +-------------------------------------------------------------------*/
  154. mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
  155. mtdcr (uic2er, 0x00000000); /* disable all interrupts */
  156. mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
  157. mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
  158. mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
  159. mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  160. mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
  161. mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
  162. mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
  163. mtdcr (uic1er, 0x00000000); /* disable all interrupts */
  164. mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
  165. mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
  166. mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
  167. mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  168. mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
  169. mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
  170. mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
  171. mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
  172. /* Except cascade UIC0 and UIC1 */
  173. mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
  174. mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
  175. mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
  176. mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  177. mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
  178. mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
  179. /*
  180. * Note: Some cores are still in reset when the chip starts, so
  181. * take them out of reset
  182. */
  183. mtsdr(SDR0_SRST, 0);
  184. /* Configure 405EX for NAND usage */
  185. val = SDR0_CUST0_MUX_NDFC_SEL |
  186. SDR0_CUST0_NDFC_ENABLE |
  187. SDR0_CUST0_NDFC_BW_8_BIT |
  188. SDR0_CUST0_NRB_BUSY |
  189. (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
  190. mtsdr(SDR0_CUST0, val);
  191. /*
  192. * Configure PFC (Pin Function Control) registers
  193. * -> Enable USB
  194. */
  195. val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
  196. mtsdr(SDR0_PFC1, val);
  197. /*
  198. * Configure FPGA register with PCIe reset
  199. */
  200. out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
  201. mdelay(50);
  202. out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
  203. return 0;
  204. }
  205. int misc_init_r(void)
  206. {
  207. #ifdef CONFIG_ENV_IS_IN_FLASH
  208. /* Monitor protection ON by default */
  209. flash_protect(FLAG_PROTECT_SET,
  210. -CONFIG_SYS_MONITOR_LEN,
  211. 0xffffffff,
  212. &flash_info[0]);
  213. #endif
  214. return 0;
  215. }
  216. static int is_405exr(void)
  217. {
  218. u32 pvr = get_pvr();
  219. if (pvr & 0x00000004)
  220. return 0; /* bit 2 set -> 405EX */
  221. return 1; /* bit 2 cleared -> 405EXr */
  222. }
  223. int board_emac_count(void)
  224. {
  225. /*
  226. * 405EXr only has one EMAC interface, 405EX has two
  227. */
  228. if (is_405exr())
  229. return 1;
  230. else
  231. return 2;
  232. }
  233. static int board_pcie_count(void)
  234. {
  235. /*
  236. * 405EXr only has one EMAC interface, 405EX has two
  237. */
  238. if (is_405exr())
  239. return 1;
  240. else
  241. return 2;
  242. }
  243. int checkboard (void)
  244. {
  245. char *s = getenv("serial#");
  246. if (is_405exr())
  247. printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
  248. else
  249. printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
  250. if (s != NULL) {
  251. puts(", serial# ");
  252. puts(s);
  253. }
  254. putc('\n');
  255. return (0);
  256. }
  257. /*************************************************************************
  258. * pci_pre_init
  259. *
  260. * This routine is called just prior to registering the hose and gives
  261. * the board the opportunity to check things. Returning a value of zero
  262. * indicates that things are bad & PCI initialization should be aborted.
  263. *
  264. * Different boards may wish to customize the pci controller structure
  265. * (add regions, override default access routines, etc) or perform
  266. * certain pre-initialization actions.
  267. *
  268. ************************************************************************/
  269. #if defined(CONFIG_PCI)
  270. int pci_pre_init(struct pci_controller * hose )
  271. {
  272. return 0;
  273. }
  274. #endif /* defined(CONFIG_PCI) */
  275. #ifdef CONFIG_PCI
  276. static struct pci_controller pcie_hose[2] = {{0},{0}};
  277. void pcie_setup_hoses(int busno)
  278. {
  279. struct pci_controller *hose;
  280. int i, bus;
  281. int ret = 0;
  282. bus = busno;
  283. char *env;
  284. unsigned int delay;
  285. for (i = 0; i < board_pcie_count(); i++) {
  286. if (is_end_point(i))
  287. ret = ppc4xx_init_pcie_endport(i);
  288. else
  289. ret = ppc4xx_init_pcie_rootport(i);
  290. if (ret) {
  291. printf("PCIE%d: initialization as %s failed\n", i,
  292. is_end_point(i) ? "endpoint" : "root-complex");
  293. continue;
  294. }
  295. hose = &pcie_hose[i];
  296. hose->first_busno = bus;
  297. hose->last_busno = bus;
  298. hose->current_busno = bus;
  299. /* setup mem resource */
  300. pci_set_region(hose->regions + 0,
  301. CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
  302. CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
  303. CONFIG_SYS_PCIE_MEMSIZE,
  304. PCI_REGION_MEM);
  305. hose->region_count = 1;
  306. pci_register_hose(hose);
  307. if (is_end_point(i)) {
  308. ppc4xx_setup_pcie_endpoint(hose, i);
  309. /*
  310. * Reson for no scanning is endpoint can not generate
  311. * upstream configuration accesses.
  312. */
  313. } else {
  314. ppc4xx_setup_pcie_rootpoint(hose, i);
  315. env = getenv ("pciscandelay");
  316. if (env != NULL) {
  317. delay = simple_strtoul(env, NULL, 10);
  318. if (delay > 5)
  319. printf("Warning, expect noticable delay before "
  320. "PCIe scan due to 'pciscandelay' value!\n");
  321. mdelay(delay * 1000);
  322. }
  323. /*
  324. * Config access can only go down stream
  325. */
  326. hose->last_busno = pci_hose_scan(hose);
  327. bus = hose->last_busno + 1;
  328. }
  329. }
  330. }
  331. #endif
  332. #if defined(CONFIG_POST)
  333. /*
  334. * Returns 1 if keys pressed to start the power-on long-running tests
  335. * Called from board_init_f().
  336. */
  337. int post_hotkeys_pressed(void)
  338. {
  339. return 0; /* No hotkeys supported */
  340. }
  341. #endif /* CONFIG_POST */