ebony.c 9.2 KB

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  1. /*
  2. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/processor.h>
  24. #include <spd_sdram.h>
  25. #define BOOT_SMALL_FLASH 32 /* 00100000 */
  26. #define FLASH_ONBD_N 2 /* 00000010 */
  27. #define FLASH_SRAM_SEL 1 /* 00000001 */
  28. DECLARE_GLOBAL_DATA_PTR;
  29. long int fixed_sdram(void);
  30. int board_early_init_f(void)
  31. {
  32. uint reg;
  33. unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
  34. unsigned char status;
  35. /*--------------------------------------------------------------------
  36. * Setup the external bus controller/chip selects
  37. *-------------------------------------------------------------------*/
  38. mtdcr(ebccfga, xbcfg);
  39. reg = mfdcr(ebccfgd);
  40. mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
  41. mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
  42. mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
  43. mtebc(pb7ap, 0x01015280); /* FPGA registers */
  44. mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
  45. /* read FPGA_REG0 and set the bus controller */
  46. status = *fpga_base;
  47. if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
  48. mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
  49. mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
  50. mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
  51. mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
  52. } else {
  53. mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
  54. mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
  55. /* set CS2 if FLASH_ONBD_N == 0 */
  56. if (!(status & FLASH_ONBD_N)) {
  57. mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
  58. mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
  59. }
  60. }
  61. /*--------------------------------------------------------------------
  62. * Setup the interrupt controller polarities, triggers, etc.
  63. *-------------------------------------------------------------------*/
  64. mtdcr(uic0sr, 0xffffffff); /* clear all */
  65. mtdcr(uic0er, 0x00000000); /* disable all */
  66. mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
  67. mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
  68. mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
  69. mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  70. mtdcr(uic0sr, 0xffffffff); /* clear all */
  71. mtdcr(uic1sr, 0xffffffff); /* clear all */
  72. mtdcr(uic1er, 0x00000000); /* disable all */
  73. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  74. mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
  75. mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
  76. mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  77. mtdcr(uic1sr, 0xffffffff); /* clear all */
  78. return 0;
  79. }
  80. int checkboard(void)
  81. {
  82. char *s = getenv("serial#");
  83. printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
  84. if (s != NULL) {
  85. puts(", serial# ");
  86. puts(s);
  87. }
  88. putc('\n');
  89. return (0);
  90. }
  91. phys_size_t initdram(int board_type)
  92. {
  93. long dram_size = 0;
  94. #if defined(CONFIG_SPD_EEPROM)
  95. dram_size = spd_sdram();
  96. #else
  97. dram_size = fixed_sdram();
  98. #endif
  99. return dram_size;
  100. }
  101. #if !defined(CONFIG_SPD_EEPROM)
  102. /*************************************************************************
  103. * fixed sdram init -- doesn't use serial presence detect.
  104. *
  105. * Assumes: 128 MB, non-ECC, non-registered
  106. * PLB @ 133 MHz
  107. *
  108. ************************************************************************/
  109. long int fixed_sdram(void)
  110. {
  111. uint reg;
  112. /*--------------------------------------------------------------------
  113. * Setup some default
  114. *------------------------------------------------------------------*/
  115. mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
  116. mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
  117. mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
  118. mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
  119. mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
  120. /*--------------------------------------------------------------------
  121. * Setup for board-specific specific mem
  122. *------------------------------------------------------------------*/
  123. /*
  124. * Following for CAS Latency = 2.5 @ 133 MHz PLB
  125. */
  126. mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
  127. mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
  128. /* RA=10 RD=3 */
  129. mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
  130. mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
  131. mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
  132. udelay(400); /* Delay 200 usecs (min) */
  133. /*--------------------------------------------------------------------
  134. * Enable the controller, then wait for DCEN to complete
  135. *------------------------------------------------------------------*/
  136. mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
  137. for (;;) {
  138. mfsdram(mem_mcsts, reg);
  139. if (reg & 0x80000000)
  140. break;
  141. }
  142. return (128 * 1024 * 1024); /* 128 MB */
  143. }
  144. #endif /* !defined(CONFIG_SPD_EEPROM) */
  145. /*************************************************************************
  146. * pci_pre_init
  147. *
  148. * This routine is called just prior to registering the hose and gives
  149. * the board the opportunity to check things. Returning a value of zero
  150. * indicates that things are bad & PCI initialization should be aborted.
  151. *
  152. * Different boards may wish to customize the pci controller structure
  153. * (add regions, override default access routines, etc) or perform
  154. * certain pre-initialization actions.
  155. *
  156. ************************************************************************/
  157. #if defined(CONFIG_PCI)
  158. int pci_pre_init(struct pci_controller *hose)
  159. {
  160. unsigned long strap;
  161. /*--------------------------------------------------------------------------+
  162. * The ebony board is always configured as the host & requires the
  163. * PCI arbiter to be enabled.
  164. *--------------------------------------------------------------------------*/
  165. strap = mfdcr(cpc0_strp1);
  166. if ((strap & 0x00100000) == 0) {
  167. printf("PCI: CPC0_STRP1[PAE] not set.\n");
  168. return 0;
  169. }
  170. return 1;
  171. }
  172. #endif /* defined(CONFIG_PCI) */
  173. /*************************************************************************
  174. * pci_target_init
  175. *
  176. * The bootstrap configuration provides default settings for the pci
  177. * inbound map (PIM). But the bootstrap config choices are limited and
  178. * may not be sufficient for a given board.
  179. *
  180. ************************************************************************/
  181. #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
  182. void pci_target_init(struct pci_controller *hose)
  183. {
  184. /*--------------------------------------------------------------------------+
  185. * Disable everything
  186. *--------------------------------------------------------------------------*/
  187. out32r(PCIX0_PIM0SA, 0); /* disable */
  188. out32r(PCIX0_PIM1SA, 0); /* disable */
  189. out32r(PCIX0_PIM2SA, 0); /* disable */
  190. out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
  191. /*--------------------------------------------------------------------------+
  192. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
  193. * options to not support sizes such as 128/256 MB.
  194. *--------------------------------------------------------------------------*/
  195. out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
  196. out32r(PCIX0_PIM0LAH, 0);
  197. out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
  198. out32r(PCIX0_BAR0, 0);
  199. /*--------------------------------------------------------------------------+
  200. * Program the board's subsystem id/vendor id
  201. *--------------------------------------------------------------------------*/
  202. out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
  203. out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
  204. out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
  205. }
  206. #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
  207. /*************************************************************************
  208. * is_pci_host
  209. *
  210. * This routine is called to determine if a pci scan should be
  211. * performed. With various hardware environments (especially cPCI and
  212. * PPMC) it's insufficient to depend on the state of the arbiter enable
  213. * bit in the strap register, or generic host/adapter assumptions.
  214. *
  215. * Rather than hard-code a bad assumption in the general 440 code, the
  216. * 440 pci code requires the board to decide at runtime.
  217. *
  218. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  219. *
  220. *
  221. ************************************************************************/
  222. #if defined(CONFIG_PCI)
  223. int is_pci_host(struct pci_controller *hose)
  224. {
  225. /* The ebony board is always configured as host. */
  226. return (1);
  227. }
  228. #endif /* defined(CONFIG_PCI) */