init.S 3.6 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <ppc_asm.tmpl>
  26. #include <config.h>
  27. #include <asm-ppc/mmu.h>
  28. /**************************************************************************
  29. * TLB TABLE
  30. *
  31. * This table is used by the cpu boot code to setup the initial tlb
  32. * entries. Rather than make broad assumptions in the cpu source tree,
  33. * this table lets each board set things up however they like.
  34. *
  35. * Pointer to the table is returned in r1
  36. *
  37. *************************************************************************/
  38. .section .bootpg,"ax"
  39. .globl tlbtab
  40. tlbtab:
  41. tlbtab_start
  42. /*
  43. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  44. * speed up boot process. It is patched after relocation to enable SA_I
  45. */
  46. #ifndef CONFIG_NAND_SPL
  47. tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
  48. #else
  49. tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
  50. tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
  51. #endif
  52. /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  53. tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
  54. /* PCI base & peripherals */
  55. tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
  56. tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
  57. tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
  58. /* PCI */
  59. tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
  60. tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
  61. tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
  62. tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
  63. /* USB 2.0 Device */
  64. tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
  65. tlbtab_end
  66. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  67. /*
  68. * For NAND booting the first TLB has to be reconfigured to full size
  69. * and with caching disabled after running from RAM!
  70. */
  71. #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
  72. #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
  73. #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
  74. .globl reconfig_tlb0
  75. reconfig_tlb0:
  76. sync
  77. isync
  78. addi r4,r0,0x0000 /* TLB entry #0 */
  79. lis r5,TLB00@h
  80. ori r5,r5,TLB00@l
  81. tlbwe r5,r4,0x0000 /* Save it out */
  82. lis r5,TLB01@h
  83. ori r5,r5,TLB01@l
  84. tlbwe r5,r4,0x0001 /* Save it out */
  85. lis r5,TLB02@h
  86. ori r5,r5,TLB02@l
  87. tlbwe r5,r4,0x0002 /* Save it out */
  88. sync
  89. isync
  90. blr
  91. #endif