memory.c 3.0 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /* define DEBUG for debugging output (obviously ;-)) */
  24. #if 0
  25. #define DEBUG
  26. #endif
  27. #include <common.h>
  28. #include <asm/processor.h>
  29. #include <asm/io.h>
  30. #include <asm/gpio.h>
  31. extern void board_pll_init_f(void);
  32. #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  33. static void cram_bcr_write(u32 wr_val)
  34. {
  35. wr_val <<= 2;
  36. /* set CRAM_CRE to 1 */
  37. gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
  38. /* Write BCR to CRAM on CS1 */
  39. out32(wr_val + 0x00200000, 0);
  40. debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
  41. /* Write BCR to CRAM on CS2 */
  42. out32(wr_val + 0x02200000, 0);
  43. debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
  44. sync();
  45. eieio();
  46. /* set CRAM_CRE back to 0 (normal operation) */
  47. gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
  48. return;
  49. }
  50. #endif
  51. phys_size_t initdram(int board_type)
  52. {
  53. #if defined(CONFIG_NAND_SPL)
  54. u32 reg;
  55. /* don't reinit PLL when booting via I2C bootstrap option */
  56. mfsdr(SDR_PINSTP, reg);
  57. if (reg != 0xf0000000)
  58. board_pll_init_f();
  59. #endif
  60. #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  61. int i;
  62. u32 val;
  63. /* 1. EBC need to program READY, CLK, ADV for ASync mode */
  64. gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  65. gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  66. gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  67. gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
  68. /* 2. EBC in Async mode */
  69. mtebc(pb1ap, 0x078F1EC0);
  70. mtebc(pb2ap, 0x078F1EC0);
  71. mtebc(pb1cr, 0x000BC000);
  72. mtebc(pb2cr, 0x020BC000);
  73. /* 3. Set CRAM in Sync mode */
  74. cram_bcr_write(0x7012); /* CRAM burst setting */
  75. /* 4. EBC in Sync mode */
  76. mtebc(pb1ap, 0x9C0201C0);
  77. mtebc(pb2ap, 0x9C0201C0);
  78. /* Set GPIO pins back to alternate function */
  79. gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  80. gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  81. /* Config EBC to use RDY */
  82. mfsdr(sdrultra0, val);
  83. mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
  84. /* Wait a short while, since for NAND booting this is too fast */
  85. for (i=0; i<200000; i++)
  86. ;
  87. #endif
  88. return (CONFIG_SYS_MBYTES_RAM << 20);
  89. }