acadia.c 3.3 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/processor.h>
  25. extern void board_pll_init_f(void);
  26. static void acadia_gpio_init(void)
  27. {
  28. /*
  29. * GPIO0 setup (select GPIO or alternate function)
  30. */
  31. out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
  32. out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
  33. out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
  34. out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
  35. out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
  36. out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
  37. out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
  38. /*
  39. * Ultra (405EZ) was nice enough to add another GPIO controller
  40. */
  41. out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
  42. out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
  43. out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
  44. out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
  45. out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
  46. out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
  47. out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
  48. }
  49. int board_early_init_f(void)
  50. {
  51. unsigned int reg;
  52. #if !defined(CONFIG_NAND_U_BOOT)
  53. /* don't reinit PLL when booting via I2C bootstrap option */
  54. mfsdr(SDR_PINSTP, reg);
  55. if (reg != 0xf0000000)
  56. board_pll_init_f();
  57. #endif
  58. acadia_gpio_init();
  59. /* Configure 405EZ for NAND usage */
  60. mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
  61. mfsdr(sdrultra0, reg);
  62. reg &= ~SDR_ULTRA0_CSN_MASK;
  63. reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
  64. SDR_ULTRA0_NDGPIOBP |
  65. SDR_ULTRA0_EBCRDYEN |
  66. SDR_ULTRA0_NFSRSTEN;
  67. mtsdr(sdrultra0, reg);
  68. /* USB Host core needs this bit set */
  69. mfsdr(sdrultra1, reg);
  70. mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
  71. mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
  72. mtdcr(uicer, 0x00000000); /* disable all ints */
  73. mtdcr(uiccr, 0x00000010);
  74. mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
  75. mtdcr(uictr, 0x00000010); /* set int trigger levels */
  76. mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
  77. return 0;
  78. }
  79. int misc_init_f(void)
  80. {
  81. /* Set EPLD to take PHY out of reset */
  82. out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
  83. udelay(100000);
  84. return 0;
  85. }
  86. /*
  87. * Check Board Identity:
  88. */
  89. int checkboard(void)
  90. {
  91. char *s = getenv("serial#");
  92. u8 rev;
  93. rev = in8(CONFIG_SYS_CPLD_BASE + 0);
  94. printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
  95. if (s != NULL) {
  96. puts(", serial# ");
  97. puts(s);
  98. }
  99. putc('\n');
  100. return (0);
  101. }