flash.c 23 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  4. *
  5. * (C) Copyright 2001-2004
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <linux/byteorder/swab.h>
  28. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  29. /* Board support for 1 or 2 flash devices */
  30. #define FLASH_PORT_WIDTH8
  31. typedef unsigned char FLASH_PORT_WIDTH;
  32. typedef volatile unsigned char FLASH_PORT_WIDTHV;
  33. #define SWAP(x) (x)
  34. /* Intel-compatible flash ID */
  35. #define INTEL_COMPAT 0x89
  36. #define INTEL_ALT 0xB0
  37. /* Intel-compatible flash commands */
  38. #define INTEL_PROGRAM 0x10
  39. #define INTEL_ERASE 0x20
  40. #define INTEL_CLEAR 0x50
  41. #define INTEL_LOCKBIT 0x60
  42. #define INTEL_PROTECT 0x01
  43. #define INTEL_STATUS 0x70
  44. #define INTEL_READID 0x90
  45. #define INTEL_CONFIRM 0xD0
  46. #define INTEL_RESET 0xFF
  47. /* Intel-compatible flash status bits */
  48. #define INTEL_FINISHED 0x80
  49. #define INTEL_OK 0x80
  50. #define FPW FLASH_PORT_WIDTH
  51. #define FPWV FLASH_PORT_WIDTHV
  52. #define FLASH_CYCLE1 0x0555
  53. #define FLASH_CYCLE2 0x02aa
  54. #define WR_BLOCK 0x20
  55. /*-----------------------------------------------------------------------
  56. * Functions
  57. */
  58. static ulong flash_get_size (FPW * addr, flash_info_t * info);
  59. static int write_data (flash_info_t * info, ulong dest, FPW data);
  60. static int write_data_block (flash_info_t * info, ulong src, ulong dest);
  61. static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
  62. static void flash_get_offsets (ulong base, flash_info_t * info);
  63. void inline spin_wheel (void);
  64. static void flash_sync_real_protect (flash_info_t * info);
  65. static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
  66. static unsigned char same_chip_banks (int bank1, int bank2);
  67. /*-----------------------------------------------------------------------
  68. */
  69. unsigned long flash_init (void)
  70. {
  71. int i;
  72. ulong size = 0;
  73. ulong fsize = 0;
  74. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
  75. memset (&flash_info[i], 0, sizeof (flash_info_t));
  76. switch (i) {
  77. case 0:
  78. flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
  79. &flash_info[i]);
  80. flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
  81. break;
  82. case 1:
  83. flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
  84. &flash_info[i]);
  85. fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
  86. flash_get_offsets (fsize, &flash_info[i]);
  87. break;
  88. case 2:
  89. flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
  90. &flash_info[i]);
  91. flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
  92. break;
  93. case 3:
  94. flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
  95. &flash_info[i]);
  96. fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
  97. flash_get_offsets (fsize, &flash_info[i]);
  98. break;
  99. default:
  100. panic ("configured to many flash banks!\n");
  101. break;
  102. }
  103. size += flash_info[i].size;
  104. /* get the h/w and s/w protection status in sync */
  105. flash_sync_real_protect(&flash_info[i]);
  106. }
  107. /* Protect monitor and environment sectors
  108. */
  109. #if defined (CONFIG_SYS_AMD_BOOT)
  110. flash_protect (FLAG_PROTECT_SET,
  111. CONFIG_SYS_MONITOR_BASE,
  112. CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
  113. &flash_info[2]);
  114. flash_protect (FLAG_PROTECT_SET,
  115. CONFIG_SYS_INTEL_BASE,
  116. CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
  117. &flash_info[1]);
  118. #else
  119. flash_protect (FLAG_PROTECT_SET,
  120. CONFIG_SYS_MONITOR_BASE,
  121. CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
  122. &flash_info[3]);
  123. flash_protect (FLAG_PROTECT_SET,
  124. CONFIG_SYS_AMD_BASE,
  125. CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
  126. #endif
  127. flash_protect (FLAG_PROTECT_SET,
  128. CONFIG_ENV1_ADDR,
  129. CONFIG_ENV1_ADDR + CONFIG_ENV1_SIZE - 1, &flash_info[1]);
  130. flash_protect (FLAG_PROTECT_SET,
  131. CONFIG_ENV_ADDR,
  132. CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[3]);
  133. return size;
  134. }
  135. /*-----------------------------------------------------------------------
  136. */
  137. static void flash_get_offsets (ulong base, flash_info_t * info)
  138. {
  139. int i;
  140. if (info->flash_id == FLASH_UNKNOWN)
  141. return;
  142. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
  143. for (i = 0; i < info->sector_count; i++) {
  144. info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
  145. info->protect[i] = 0;
  146. }
  147. }
  148. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
  149. for (i = 0; i < info->sector_count; i++) {
  150. info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
  151. }
  152. }
  153. }
  154. /*-----------------------------------------------------------------------
  155. */
  156. void flash_print_info (flash_info_t * info)
  157. {
  158. int i;
  159. if (info->flash_id == FLASH_UNKNOWN) {
  160. printf ("missing or unknown FLASH type\n");
  161. return;
  162. }
  163. switch (info->flash_id & FLASH_VENDMASK) {
  164. case FLASH_MAN_INTEL:
  165. printf ("INTEL ");
  166. break;
  167. case FLASH_MAN_AMD:
  168. printf ("AMD ");
  169. break;
  170. default:
  171. printf ("Unknown Vendor ");
  172. break;
  173. }
  174. switch (info->flash_id & FLASH_TYPEMASK) {
  175. case FLASH_28F128J3A:
  176. printf ("28F128J3A\n");
  177. break;
  178. case FLASH_AM040:
  179. printf ("AMD29F040B\n");
  180. break;
  181. default:
  182. printf ("Unknown Chip Type\n");
  183. break;
  184. }
  185. printf (" Size: %ld MB in %d Sectors\n",
  186. info->size >> 20, info->sector_count);
  187. printf (" Sector Start Addresses:");
  188. for (i = 0; i < info->sector_count; ++i) {
  189. if ((i % 5) == 0)
  190. printf ("\n ");
  191. printf (" %08lX%s",
  192. info->start[i], info->protect[i] ? " (RO)" : " ");
  193. }
  194. printf ("\n");
  195. return;
  196. }
  197. /*
  198. * The following code cannot be run from FLASH!
  199. */
  200. static ulong flash_get_size (FPW * addr, flash_info_t * info)
  201. {
  202. FPWV value;
  203. static int amd = 0;
  204. /* Write auto select command: read Manufacturer ID */
  205. /* Write auto select command sequence and test FLASH answer */
  206. addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
  207. __asm__ ("sync");
  208. addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
  209. __asm__ ("sync");
  210. addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
  211. __asm__ ("sync");
  212. udelay (100);
  213. switch (addr[0] & 0xff) {
  214. case (uchar) AMD_MANUFACT:
  215. info->flash_id = FLASH_MAN_AMD;
  216. value = addr[1];
  217. break;
  218. case (uchar) INTEL_MANUFACT:
  219. info->flash_id = FLASH_MAN_INTEL;
  220. value = addr[2];
  221. break;
  222. default:
  223. printf ("unknown\n");
  224. info->flash_id = FLASH_UNKNOWN;
  225. info->sector_count = 0;
  226. info->size = 0;
  227. addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
  228. return (0); /* no or unknown flash */
  229. }
  230. switch (value) {
  231. case (FPW) INTEL_ID_28F128J3A:
  232. info->flash_id += FLASH_28F128J3A;
  233. info->sector_count = 64;
  234. info->size = 0x00800000; /* => 16 MB */
  235. break;
  236. case (FPW) AMD_ID_LV040B:
  237. info->flash_id += FLASH_AM040;
  238. if (amd == 0) {
  239. info->sector_count = 7;
  240. info->size = 0x00070000; /* => 448 KB */
  241. amd = 1;
  242. } else {
  243. /* for Environment settings */
  244. info->sector_count = 1;
  245. info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */
  246. amd = 0;
  247. }
  248. break;
  249. default:
  250. info->flash_id = FLASH_UNKNOWN;
  251. break;
  252. }
  253. if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
  254. printf ("** ERROR: sector count %d > max (%d) **\n",
  255. info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
  256. info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
  257. }
  258. if (value == (FPW) INTEL_ID_28F128J3A)
  259. addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
  260. else
  261. addr[0] = (FPW) 0x00F000F0; /* restore read mode */
  262. return (info->size);
  263. }
  264. /*
  265. * This function gets the u-boot flash sector protection status
  266. * (flash_info_t.protect[]) in sync with the sector protection
  267. * status stored in hardware.
  268. */
  269. static void flash_sync_real_protect (flash_info_t * info)
  270. {
  271. int i;
  272. switch (info->flash_id & FLASH_TYPEMASK) {
  273. case FLASH_28F128J3A:
  274. for (i = 0; i < info->sector_count; ++i) {
  275. info->protect[i] = intel_sector_protected(info, i);
  276. }
  277. break;
  278. case FLASH_AM040:
  279. default:
  280. /* no h/w protect support */
  281. break;
  282. }
  283. }
  284. /*
  285. * checks if "sector" in bank "info" is protected. Should work on intel
  286. * strata flash chips 28FxxxJ3x in 8-bit mode.
  287. * Returns 1 if sector is protected (or timed-out while trying to read
  288. * protection status), 0 if it is not.
  289. */
  290. static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
  291. {
  292. FPWV *addr;
  293. FPWV *lock_conf_addr;
  294. ulong start;
  295. unsigned char ret;
  296. /*
  297. * first, wait for the WSM to be finished. The rationale for
  298. * waiting for the WSM to become idle for at most
  299. * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
  300. * because of: (1) erase, (2) program or (3) lock bit
  301. * configuration. So we just wait for the longest timeout of
  302. * the (1)-(3), i.e. the erase timeout.
  303. */
  304. /* wait at least 35ns (W12) before issuing Read Status Register */
  305. udelay(1);
  306. addr = (FPWV *) info->start[sector];
  307. *addr = (FPW) INTEL_STATUS;
  308. start = get_timer (0);
  309. while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
  310. if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
  311. *addr = (FPW) INTEL_RESET; /* restore read mode */
  312. printf("WSM busy too long, can't get prot status\n");
  313. return 1;
  314. }
  315. }
  316. /* issue the Read Identifier Codes command */
  317. *addr = (FPW) INTEL_READID;
  318. /* wait at least 35ns (W12) before reading */
  319. udelay(1);
  320. /* Intel example code uses offset of 4 for 8-bit flash */
  321. lock_conf_addr = (FPWV *) info->start[sector] + 4;
  322. ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
  323. /* put flash back in read mode */
  324. *addr = (FPW) INTEL_RESET;
  325. return ret;
  326. }
  327. /*
  328. * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they
  329. * are and 0 otherwise.
  330. */
  331. static unsigned char same_chip_banks (int bank1, int bank2)
  332. {
  333. unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
  334. {1, 1, 0, 0},
  335. {1, 1, 0, 0},
  336. {0, 0, 1, 1},
  337. {0, 0, 1, 1}
  338. };
  339. return same_chip[bank1][bank2];
  340. }
  341. /*-----------------------------------------------------------------------
  342. */
  343. int flash_erase (flash_info_t * info, int s_first, int s_last)
  344. {
  345. int flag, prot, sect;
  346. ulong type, start, last;
  347. int rcode = 0, intel = 0;
  348. if ((s_first < 0) || (s_first > s_last)) {
  349. if (info->flash_id == FLASH_UNKNOWN)
  350. printf ("- missing\n");
  351. else
  352. printf ("- no sectors to erase\n");
  353. return 1;
  354. }
  355. type = (info->flash_id & FLASH_VENDMASK);
  356. if ((type != FLASH_MAN_INTEL)) {
  357. type = (info->flash_id & FLASH_VENDMASK);
  358. if ((type != FLASH_MAN_AMD)) {
  359. printf ("Can't erase unknown flash type %08lx - aborted\n",
  360. info->flash_id);
  361. return 1;
  362. }
  363. }
  364. if (type == FLASH_MAN_INTEL)
  365. intel = 1;
  366. prot = 0;
  367. for (sect = s_first; sect <= s_last; ++sect) {
  368. if (info->protect[sect]) {
  369. prot++;
  370. }
  371. }
  372. if (prot) {
  373. printf ("- Warning: %d protected sectors will not be erased!\n", prot);
  374. } else {
  375. printf ("\n");
  376. }
  377. start = get_timer (0);
  378. last = start;
  379. /* Disable interrupts which might cause a timeout here */
  380. flag = disable_interrupts ();
  381. /* Start erase on unprotected sectors */
  382. for (sect = s_first; sect <= s_last; sect++) {
  383. if (info->protect[sect] == 0) { /* not protected */
  384. FPWV *addr = (FPWV *) (info->start[sect]);
  385. FPW status;
  386. printf ("Erasing sector %2d ... ", sect);
  387. /* arm simple, non interrupt dependent timer */
  388. start = get_timer (0);
  389. if (intel) {
  390. *addr = (FPW) 0x00500050; /* clear status register */
  391. *addr = (FPW) 0x00200020; /* erase setup */
  392. *addr = (FPW) 0x00D000D0; /* erase confirm */
  393. } else {
  394. FPWV *base; /* first address in bank */
  395. base = (FPWV *) (CONFIG_SYS_AMD_BASE);
  396. base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
  397. base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
  398. base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
  399. base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
  400. base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
  401. *addr = (FPW) 0x00300030; /* erase sector */
  402. }
  403. while (((status =
  404. *addr) & (FPW) 0x00800080) !=
  405. (FPW) 0x00800080) {
  406. if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
  407. printf ("Timeout\n");
  408. if (intel) {
  409. *addr = (FPW) 0x00B000B0; /* suspend erase */
  410. *addr = (FPW) 0x00FF00FF; /* reset to read mode */
  411. } else
  412. *addr = (FPW) 0x00F000F0; /* reset to read mode */
  413. rcode = 1;
  414. break;
  415. }
  416. }
  417. if (intel) {
  418. *addr = (FPW) 0x00500050; /* clear status register cmd. */
  419. *addr = (FPW) 0x00FF00FF; /* resest to read mode */
  420. } else
  421. *addr = (FPW) 0x00F000F0; /* reset to read mode */
  422. printf (" done\n");
  423. }
  424. }
  425. return rcode;
  426. }
  427. /*-----------------------------------------------------------------------
  428. * Copy memory to flash, returns:
  429. * 0 - OK
  430. * 1 - write timeout
  431. * 2 - Flash not erased
  432. * 4 - Flash not identified
  433. */
  434. int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  435. {
  436. if (info->flash_id == FLASH_UNKNOWN) {
  437. return 4;
  438. }
  439. switch (info->flash_id & FLASH_VENDMASK) {
  440. case FLASH_MAN_AMD:
  441. {
  442. FPW data = 0; /* 16 or 32 bit word, matches flash bus width */
  443. int bytes; /* number of bytes to program in current word */
  444. int left; /* number of bytes left to program */
  445. int i, res;
  446. for (left = cnt, res = 0;
  447. left > 0 && res == 0;
  448. addr += sizeof (data), left -=
  449. sizeof (data) - bytes) {
  450. bytes = addr & (sizeof (data) - 1);
  451. addr &= ~(sizeof (data) - 1);
  452. /* combine source and destination data so can program
  453. * an entire word of 16 or 32 bits
  454. */
  455. for (i = 0; i < sizeof (data); i++) {
  456. data <<= 8;
  457. if (i < bytes || i - bytes >= left)
  458. data += *((uchar *) addr + i);
  459. else
  460. data += *src++;
  461. }
  462. res = write_word_amd (info, (FPWV *) addr,
  463. data);
  464. }
  465. return res;
  466. } /* case FLASH_MAN_AMD */
  467. case FLASH_MAN_INTEL:
  468. {
  469. ulong cp, wp;
  470. FPW data;
  471. int count, i, l, rc, port_width;
  472. /* get lower word aligned address */
  473. wp = addr;
  474. port_width = 1;
  475. /*
  476. * handle unaligned start bytes
  477. */
  478. if ((l = addr - wp) != 0) {
  479. data = 0;
  480. for (i = 0, cp = wp; i < l; ++i, ++cp) {
  481. data = (data << 8) | (*(uchar *) cp);
  482. }
  483. for (; i < port_width && cnt > 0; ++i) {
  484. data = (data << 8) | *src++;
  485. --cnt;
  486. ++cp;
  487. }
  488. for (; cnt == 0 && i < port_width; ++i, ++cp)
  489. data = (data << 8) | (*(uchar *) cp);
  490. if ((rc =
  491. write_data (info, wp, SWAP (data))) != 0)
  492. return (rc);
  493. wp += port_width;
  494. }
  495. if (cnt > WR_BLOCK) {
  496. /*
  497. * handle word aligned part
  498. */
  499. count = 0;
  500. while (cnt >= WR_BLOCK) {
  501. if ((rc =
  502. write_data_block (info,
  503. (ulong) src,
  504. wp)) != 0)
  505. return (rc);
  506. wp += WR_BLOCK;
  507. src += WR_BLOCK;
  508. cnt -= WR_BLOCK;
  509. if (count++ > 0x800) {
  510. spin_wheel ();
  511. count = 0;
  512. }
  513. }
  514. }
  515. if (cnt < WR_BLOCK) {
  516. /*
  517. * handle word aligned part
  518. */
  519. count = 0;
  520. while (cnt >= port_width) {
  521. data = 0;
  522. for (i = 0; i < port_width; ++i)
  523. data = (data << 8) | *src++;
  524. if ((rc =
  525. write_data (info, wp,
  526. SWAP (data))) != 0)
  527. return (rc);
  528. wp += port_width;
  529. cnt -= port_width;
  530. if (count++ > 0x800) {
  531. spin_wheel ();
  532. count = 0;
  533. }
  534. }
  535. }
  536. if (cnt == 0)
  537. return (0);
  538. /*
  539. * handle unaligned tail bytes
  540. */
  541. data = 0;
  542. for (i = 0, cp = wp; i < port_width && cnt > 0;
  543. ++i, ++cp) {
  544. data = (data << 8) | *src++;
  545. --cnt;
  546. }
  547. for (; i < port_width; ++i, ++cp)
  548. data = (data << 8) | (*(uchar *) cp);
  549. return (write_data (info, wp, SWAP (data)));
  550. } /* case FLASH_MAN_INTEL */
  551. } /* switch */
  552. return (0);
  553. }
  554. /*-----------------------------------------------------------------------
  555. * Write a word or halfword to Flash, returns:
  556. * 0 - OK
  557. * 1 - write timeout
  558. * 2 - Flash not erased
  559. */
  560. static int write_data (flash_info_t * info, ulong dest, FPW data)
  561. {
  562. FPWV *addr = (FPWV *) dest;
  563. ulong start;
  564. int flag;
  565. /* Check if Flash is (sufficiently) erased */
  566. if ((*addr & data) != data) {
  567. printf ("not erased at %08lx (%lx)\n", (ulong)addr, (ulong)*addr);
  568. return (2);
  569. }
  570. /* Disable interrupts which might cause a timeout here */
  571. flag = disable_interrupts ();
  572. *addr = (FPW) 0x00400040; /* write setup */
  573. *addr = data;
  574. /* arm simple, non interrupt dependent timer */
  575. start = get_timer (0);
  576. /* wait while polling the status register */
  577. while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
  578. if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
  579. *addr = (FPW) 0x00FF00FF; /* restore read mode */
  580. return (1);
  581. }
  582. }
  583. *addr = (FPW) 0x00FF00FF; /* restore read mode */
  584. return (0);
  585. }
  586. /*-----------------------------------------------------------------------
  587. * Write a word or halfword to Flash, returns:
  588. * 0 - OK
  589. * 1 - write timeout
  590. * 2 - Flash not erased
  591. */
  592. static int write_data_block (flash_info_t * info, ulong src, ulong dest)
  593. {
  594. FPWV *srcaddr = (FPWV *) src;
  595. FPWV *dstaddr = (FPWV *) dest;
  596. ulong start;
  597. int flag, i;
  598. /* Check if Flash is (sufficiently) erased */
  599. for (i = 0; i < WR_BLOCK; i++)
  600. if ((*dstaddr++ & 0xff) != 0xff) {
  601. printf ("not erased at %08lx (%lx)\n",
  602. (ulong)dstaddr, (ulong)*dstaddr);
  603. return (2);
  604. }
  605. dstaddr = (FPWV *) dest;
  606. /* Disable interrupts which might cause a timeout here */
  607. flag = disable_interrupts ();
  608. *dstaddr = (FPW) 0x00e800e8; /* write block setup */
  609. /* arm simple, non interrupt dependent timer */
  610. start = get_timer (0);
  611. /* wait while polling the status register */
  612. while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
  613. if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
  614. *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
  615. return (1);
  616. }
  617. }
  618. *dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */
  619. for (i = 0; i < WR_BLOCK; i++)
  620. *dstaddr++ = *srcaddr++;
  621. dstaddr -= 1;
  622. *dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */
  623. /* arm simple, non interrupt dependent timer */
  624. start = get_timer (0);
  625. /* wait while polling the status register */
  626. while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
  627. if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
  628. *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
  629. return (1);
  630. }
  631. }
  632. *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
  633. return (0);
  634. }
  635. /*-----------------------------------------------------------------------
  636. * Write a word to Flash for AMD FLASH
  637. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  638. * (not an individual chip) is.
  639. *
  640. * returns:
  641. * 0 - OK
  642. * 1 - write timeout
  643. * 2 - Flash not erased
  644. */
  645. static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
  646. {
  647. ulong start;
  648. int flag;
  649. int res = 0; /* result, assume success */
  650. FPWV *base; /* first address in flash bank */
  651. /* Check if Flash is (sufficiently) erased */
  652. if ((*dest & data) != data) {
  653. return (2);
  654. }
  655. base = (FPWV *) (CONFIG_SYS_AMD_BASE);
  656. /* Disable interrupts which might cause a timeout here */
  657. flag = disable_interrupts ();
  658. base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
  659. base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
  660. base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
  661. *dest = data; /* start programming the data */
  662. /* re-enable interrupts if necessary */
  663. if (flag)
  664. enable_interrupts ();
  665. start = get_timer (0);
  666. /* data polling for D7 */
  667. while (res == 0
  668. && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
  669. if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
  670. *dest = (FPW) 0x00F000F0; /* reset bank */
  671. res = 1;
  672. }
  673. }
  674. return (res);
  675. }
  676. void inline spin_wheel (void)
  677. {
  678. static int p = 0;
  679. static char w[] = "\\/-";
  680. printf ("\010%c", w[p]);
  681. (++p == 3) ? (p = 0) : 0;
  682. }
  683. /*-----------------------------------------------------------------------
  684. * Set/Clear sector's lock bit, returns:
  685. * 0 - OK
  686. * 1 - Error (timeout, voltage problems, etc.)
  687. */
  688. int flash_real_protect (flash_info_t * info, long sector, int prot)
  689. {
  690. ulong start;
  691. int i, j;
  692. int curr_bank;
  693. int bank;
  694. int rc = 0;
  695. FPWV *addr = (FPWV *) (info->start[sector]);
  696. int flag = disable_interrupts ();
  697. /*
  698. * 29F040B AMD flash does not support software protection/unprotection,
  699. * the only way to protect the AMD flash is marked it as prot bit.
  700. * This flash only support hardware protection, by supply or not supply
  701. * 12vpp to the flash
  702. */
  703. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
  704. info->protect[sector] = prot;
  705. return 0;
  706. }
  707. *addr = INTEL_CLEAR; /* Clear status register */
  708. if (prot) { /* Set sector lock bit */
  709. *addr = INTEL_LOCKBIT; /* Sector lock bit */
  710. *addr = INTEL_PROTECT; /* set */
  711. } else { /* Clear sector lock bit */
  712. *addr = INTEL_LOCKBIT; /* All sectors lock bits */
  713. *addr = INTEL_CONFIRM; /* clear */
  714. }
  715. start = get_timer (0);
  716. while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
  717. if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
  718. printf ("Flash lock bit operation timed out\n");
  719. rc = 1;
  720. break;
  721. }
  722. }
  723. if (*addr != INTEL_OK) {
  724. printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
  725. (uint) addr, (uint) * addr);
  726. rc = 1;
  727. }
  728. if (!rc)
  729. info->protect[sector] = prot;
  730. /*
  731. * Clear lock bit command clears all sectors lock bits, so
  732. * we have to restore lock bits of protected sectors.
  733. */
  734. if (!prot) {
  735. /*
  736. * re-locking must be done for all banks that belong on one
  737. * FLASH chip, as all the sectors on the chip were unlocked
  738. * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
  739. * that banks never span chips, in particular chips which
  740. * support h/w protection differently).
  741. */
  742. /* find the current bank number */
  743. curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
  744. for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
  745. if (&flash_info[j] == info) {
  746. curr_bank = j;
  747. }
  748. }
  749. if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
  750. printf("Error: can't determine bank number!\n");
  751. }
  752. for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
  753. if (!same_chip_banks(curr_bank, bank)) {
  754. continue;
  755. }
  756. info = &flash_info[bank];
  757. for (i = 0; i < info->sector_count; i++) {
  758. if (info->protect[i]) {
  759. start = get_timer (0);
  760. addr = (FPWV *) (info->start[i]);
  761. *addr = INTEL_LOCKBIT; /* Sector lock bit */
  762. *addr = INTEL_PROTECT; /* set */
  763. while ((*addr & INTEL_FINISHED) !=
  764. INTEL_FINISHED) {
  765. if (get_timer (start) >
  766. CONFIG_SYS_FLASH_UNLOCK_TOUT) {
  767. printf ("Flash lock bit operation timed out\n");
  768. rc = 1;
  769. break;
  770. }
  771. }
  772. }
  773. }
  774. }
  775. /*
  776. * get the s/w sector protection status in sync with the h/w,
  777. * in case something went wrong during the re-locking.
  778. */
  779. flash_sync_real_protect(info); /* resets flash to read mode */
  780. }
  781. if (flag)
  782. enable_interrupts ();
  783. *addr = INTEL_RESET; /* Reset to read array mode */
  784. return rc;
  785. }