intel_flash.h 7.6 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * Hacked for the marvell db64360 eval board by
  24. * Ingo Assmus <ingo.assmus@keymile.com>
  25. */
  26. /*************** DEFINES for Intel StrataFlash FLASH chip ********************/
  27. /*
  28. * acceptable chips types are:
  29. *
  30. * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
  31. */
  32. /* register addresses, valid only following an CHIP_CMD_RD_ID command */
  33. #define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
  34. #define CHIP_ADDR_REG_DEV 0x000001 /* device id */
  35. #define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
  36. #define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
  37. /* Commands */
  38. #define CHIP_CMD_RST 0xFF /* reset flash */
  39. #define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
  40. #define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
  41. #define CHIP_CMD_RD_STAT 0x70 /* read the status register */
  42. #define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
  43. #define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
  44. #define CHIP_CMD_PROG 0x40 /* program word command */
  45. #define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
  46. #define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
  47. #define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
  48. #define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
  49. #define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
  50. #define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
  51. #define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
  52. /* status register bits */
  53. #define CHIP_STAT_DPS 0x02 /* Device Protect Status */
  54. #define CHIP_STAT_VPPS 0x08 /* VPP Status */
  55. #define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
  56. #define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
  57. #define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
  58. #define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
  59. #define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
  60. CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
  61. /* ID and Lock Configuration */
  62. #define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
  63. #define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
  64. #define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
  65. /* dimensions */
  66. #define CHIP_WIDTH 2 /* chips are in 16 bit mode */
  67. #define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
  68. #define CHIP_NBLOCKS 128
  69. #define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
  70. #define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
  71. /********************** DEFINES for Hymod Flash ******************************/
  72. /*
  73. * The hymod board has 2 x 28F320J5 chips running in
  74. * 16 bit mode, for a 32 bit wide bank.
  75. */
  76. typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
  77. typedef volatile bank_word_t *bank_addr_t;
  78. typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
  79. #define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
  80. #define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
  81. #define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
  82. #define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
  83. #define BANK_NBLOCKS CHIP_NBLOCKS
  84. #define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
  85. #define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
  86. #define MAX_BANKS 1 /* only one bank possible */
  87. /* align bank addresses and sizes to bank word boundaries */
  88. #define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
  89. & ~(BANK_WIDTH - 1)))
  90. #define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
  91. (bank_size_t)(s) + (BANK_WIDTH - 1)))
  92. /* align bank addresses and sizes to bank block boundaries */
  93. #define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
  94. & ~(BANK_BLKSZ - 1)))
  95. #define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
  96. (bank_size_t)(s) + (BANK_BLKSZ - 1)))
  97. /* align bank addresses and sizes to bank boundaries */
  98. #define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
  99. & ~(BANK_SIZE - 1)))
  100. #define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
  101. (bank_size_t)(s) + (BANK_SIZE - 1)))
  102. /* add an offset to a bank address */
  103. #define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
  104. (bank_size_t)(o))
  105. /* get base address of bank b, given flash base address a */
  106. #define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
  107. (bank_size_t)(b) * BANK_SIZE)
  108. /* adjust a bank address to start of next word, block or bank */
  109. #define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
  110. BANK_WIDTH)
  111. #define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
  112. BANK_BLKSZ)
  113. #define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
  114. BANK_SIZE)
  115. /* get bank address of chip register r given a bank base address a */
  116. #define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
  117. ((bank_size_t)(r) << BANK_WSHIFT))
  118. /* make a bank address for each chip register address */
  119. #define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
  120. #define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
  121. #define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
  122. #define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
  123. /*
  124. * replicate a chip cmd/stat/rd value into each byte position within a word
  125. * so that multiple chips are accessed in a single word i/o operation
  126. *
  127. * this must be as wide as the bank_word_t type, and take into account the
  128. * chip width and bank layout
  129. */
  130. #define BANK_FILL_WORD(o) ((bank_word_t)(o))
  131. /* make a bank word value for each chip cmd/stat/rd value */
  132. /* Commands */
  133. #define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
  134. #define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
  135. #define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
  136. #define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
  137. #define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
  138. #define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
  139. #define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
  140. #define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
  141. #define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
  142. #define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
  143. #define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
  144. /* status register bits */
  145. #define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
  146. #define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
  147. #define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
  148. #define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
  149. #define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
  150. #define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
  151. #define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
  152. #define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
  153. /* ID and Lock Configuration */
  154. #define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
  155. #define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
  156. #define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)