mii.c 7.9 KB

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  1. /*
  2. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/fec.h>
  25. #include <asm/immap.h>
  26. #include <config.h>
  27. #include <net.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
  30. #undef MII_DEBUG
  31. #undef ET_DEBUG
  32. int fecpin_setclear(struct eth_device *dev, int setclear)
  33. {
  34. if (setclear) {
  35. MCFGPIO_PASPAR |= 0x0F00;
  36. MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
  37. } else {
  38. MCFGPIO_PASPAR &= 0xF0FF;
  39. MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
  40. }
  41. return 0;
  42. }
  43. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
  44. #include <miiphy.h>
  45. /* Make MII read/write commands for the FEC. */
  46. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
  47. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
  48. /* PHY identification */
  49. #define PHY_ID_LXT970 0x78100000 /* LXT970 */
  50. #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
  51. #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
  52. #define PHY_ID_QS6612 0x01814400 /* QS6612 */
  53. #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
  54. #define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
  55. #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
  56. #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
  57. #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
  58. #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
  59. #define STR_ID_LXT970 "LXT970"
  60. #define STR_ID_LXT971 "LXT971"
  61. #define STR_ID_82555 "Intel82555"
  62. #define STR_ID_QS6612 "QS6612"
  63. #define STR_ID_AMD79C784 "AMD79C784"
  64. #define STR_ID_AMD79C874VC "AMD79C874VC"
  65. #define STR_ID_LSI80225 "LSI80225"
  66. #define STR_ID_LSI80225B "LSI80225/B"
  67. #define STR_ID_DP83848VV "N83848"
  68. #define STR_ID_DP83849 "N83849"
  69. /****************************************************************************
  70. * mii_init -- Initialize the MII for MII command without ethernet
  71. * This function is a subset of eth_init
  72. ****************************************************************************
  73. */
  74. void mii_reset(struct fec_info_s *info)
  75. {
  76. volatile fec_t *fecp = (fec_t *) (info->miibase);
  77. int i;
  78. fecp->ecr = FEC_ECR_RESET;
  79. for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  80. udelay(1);
  81. }
  82. if (i == FEC_RESET_DELAY) {
  83. printf("FEC_RESET_DELAY timeout\n");
  84. }
  85. }
  86. /* send command to phy using mii, wait for result */
  87. uint mii_send(uint mii_cmd)
  88. {
  89. struct fec_info_s *info;
  90. struct eth_device *dev;
  91. volatile fec_t *ep;
  92. uint mii_reply;
  93. int j = 0;
  94. /* retrieve from register structure */
  95. dev = eth_get_dev();
  96. info = dev->priv;
  97. ep = (fec_t *) info->miibase;
  98. ep->mmfr = mii_cmd; /* command to phy */
  99. /* wait for mii complete */
  100. while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
  101. udelay(1);
  102. j++;
  103. }
  104. if (j >= MCFFEC_TOUT_LOOP) {
  105. printf("MII not complete\n");
  106. return -1;
  107. }
  108. mii_reply = ep->mmfr; /* result from phy */
  109. ep->eir = FEC_EIR_MII; /* clear MII complete */
  110. #ifdef ET_DEBUG
  111. printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
  112. __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
  113. #endif
  114. return (mii_reply & 0xffff); /* data read from phy */
  115. }
  116. #endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
  117. #if defined(CONFIG_SYS_DISCOVER_PHY)
  118. int mii_discover_phy(struct eth_device *dev)
  119. {
  120. #define MAX_PHY_PASSES 11
  121. struct fec_info_s *info = dev->priv;
  122. int phyaddr, pass;
  123. uint phyno, phytype;
  124. if (info->phyname_init)
  125. return info->phy_addr;
  126. phyaddr = -1; /* didn't find a PHY yet */
  127. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  128. if (pass > 1) {
  129. /* PHY may need more time to recover from reset.
  130. * The LXT970 needs 50ms typical, no maximum is
  131. * specified, so wait 10ms before try again.
  132. * With 11 passes this gives it 100ms to wake up.
  133. */
  134. udelay(10000); /* wait 10ms */
  135. }
  136. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  137. phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
  138. #ifdef ET_DEBUG
  139. printf("PHY type 0x%x pass %d type\n", phytype, pass);
  140. #endif
  141. if (phytype != 0xffff) {
  142. phyaddr = phyno;
  143. phytype <<= 16;
  144. phytype |=
  145. mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
  146. switch (phytype & 0xffffffff) {
  147. case PHY_ID_AMD79C874VC:
  148. strcpy(info->phy_name,
  149. STR_ID_AMD79C874VC);
  150. info->phyname_init = 1;
  151. break;
  152. default:
  153. strcpy(info->phy_name, "unknown");
  154. info->phyname_init = 1;
  155. break;
  156. }
  157. #ifdef ET_DEBUG
  158. printf("PHY @ 0x%x pass %d type ", phyno, pass);
  159. switch (phytype & 0xffffffff) {
  160. case PHY_ID_AMD79C874VC:
  161. printf(STR_ID_AMD79C874VC);
  162. break;
  163. default:
  164. printf("0x%08x\n", phytype);
  165. break;
  166. }
  167. #endif
  168. }
  169. }
  170. }
  171. if (phyaddr < 0)
  172. printf("No PHY device found.\n");
  173. return phyaddr;
  174. }
  175. #endif /* CONFIG_SYS_DISCOVER_PHY */
  176. void mii_init(void) __attribute__((weak,alias("__mii_init")));
  177. void __mii_init(void)
  178. {
  179. volatile fec_t *fecp;
  180. struct fec_info_s *info;
  181. struct eth_device *dev;
  182. int miispd = 0, i = 0;
  183. u16 autoneg = 0;
  184. /* retrieve from register structure */
  185. dev = eth_get_dev();
  186. info = dev->priv;
  187. fecp = (fec_t *) info->miibase;
  188. fecpin_setclear(dev, 1);
  189. mii_reset(info);
  190. /* We use strictly polling mode only */
  191. fecp->eimr = 0;
  192. /* Clear any pending interrupt */
  193. fecp->eir = 0xffffffff;
  194. /* Set MII speed */
  195. miispd = (gd->bus_clk / 1000000) / 5;
  196. fecp->mscr = miispd << 1;
  197. info->phy_addr = mii_discover_phy(dev);
  198. #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
  199. while (i < MCFFEC_TOUT_LOOP) {
  200. autoneg = 0;
  201. miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
  202. i++;
  203. if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
  204. break;
  205. udelay(500);
  206. }
  207. if (i >= MCFFEC_TOUT_LOOP) {
  208. printf("Auto Negotiation not complete\n");
  209. }
  210. /* adapt to the half/full speed settings */
  211. info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
  212. info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
  213. }
  214. /*****************************************************************************
  215. * Read and write a MII PHY register, routines used by MII Utilities
  216. *
  217. * FIXME: These routines are expected to return 0 on success, but mii_send
  218. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  219. * no PHY connected...
  220. * For now always return 0.
  221. * FIXME: These routines only work after calling eth_init() at least once!
  222. * Otherwise they hang in mii_send() !!! Sorry!
  223. *****************************************************************************/
  224. int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
  225. unsigned short *value)
  226. {
  227. short rdreg; /* register working value */
  228. #ifdef MII_DEBUG
  229. printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
  230. #endif
  231. rdreg = mii_send(mk_mii_read(addr, reg));
  232. *value = rdreg;
  233. #ifdef MII_DEBUG
  234. printf("0x%04x\n", *value);
  235. #endif
  236. return 0;
  237. }
  238. int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
  239. unsigned short value)
  240. {
  241. short rdreg; /* register working value */
  242. #ifdef MII_DEBUG
  243. printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
  244. #endif
  245. rdreg = mii_send(mk_mii_write(addr, reg, value));
  246. #ifdef MII_DEBUG
  247. printf("0x%04x\n", value);
  248. #endif
  249. return 0;
  250. }
  251. #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */