ddrphy_utils.c 9.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/ddr.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/ddr.h>
  12. #include <asm/arch/lpddr4_define.h>
  13. #include <asm/arch/sys_proto.h>
  14. static unsigned int g_cdd_rr_max[4];
  15. static unsigned int g_cdd_rw_max[4];
  16. static unsigned int g_cdd_wr_max[4];
  17. static unsigned int g_cdd_ww_max[4];
  18. static inline void poll_pmu_message_ready(void)
  19. {
  20. unsigned int reg;
  21. do {
  22. reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  23. } while (reg & 0x1);
  24. }
  25. static inline void ack_pmu_message_receive(void)
  26. {
  27. unsigned int reg;
  28. reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
  29. do {
  30. reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  31. } while (!(reg & 0x1));
  32. reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
  33. }
  34. static inline unsigned int get_mail(void)
  35. {
  36. unsigned int reg;
  37. poll_pmu_message_ready();
  38. reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
  39. ack_pmu_message_receive();
  40. return reg;
  41. }
  42. static inline unsigned int get_stream_message(void)
  43. {
  44. unsigned int reg, reg2;
  45. poll_pmu_message_ready();
  46. reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
  47. reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
  48. reg2 = (reg2 << 16) | reg;
  49. ack_pmu_message_receive();
  50. return reg2;
  51. }
  52. static inline void decode_major_message(unsigned int mail)
  53. {
  54. debug("[PMU Major message = 0x%08x]\n", mail);
  55. }
  56. static inline void decode_streaming_message(void)
  57. {
  58. unsigned int string_index, arg __maybe_unused;
  59. int i = 0;
  60. string_index = get_stream_message();
  61. debug("PMU String index = 0x%08x\n", string_index);
  62. while (i < (string_index & 0xffff)) {
  63. arg = get_stream_message();
  64. debug("arg[%d] = 0x%08x\n", i, arg);
  65. i++;
  66. }
  67. debug("\n");
  68. }
  69. int wait_ddrphy_training_complete(void)
  70. {
  71. unsigned int mail;
  72. while (1) {
  73. mail = get_mail();
  74. decode_major_message(mail);
  75. if (mail == 0x08) {
  76. decode_streaming_message();
  77. } else if (mail == 0x07) {
  78. debug("Training PASS\n");
  79. return 0;
  80. } else if (mail == 0xff) {
  81. debug("Training FAILED\n");
  82. return -1;
  83. }
  84. }
  85. }
  86. void ddrphy_init_set_dfi_clk(unsigned int drate)
  87. {
  88. switch (drate) {
  89. case 4000:
  90. dram_pll_init(MHZ(1000));
  91. dram_disable_bypass();
  92. break;
  93. case 3200:
  94. dram_pll_init(MHZ(800));
  95. dram_disable_bypass();
  96. break;
  97. case 3000:
  98. dram_pll_init(MHZ(750));
  99. dram_disable_bypass();
  100. break;
  101. case 2400:
  102. dram_pll_init(MHZ(600));
  103. dram_disable_bypass();
  104. break;
  105. case 1600:
  106. dram_pll_init(MHZ(400));
  107. dram_disable_bypass();
  108. break;
  109. case 1066:
  110. dram_pll_init(MHZ(266));
  111. dram_disable_bypass();
  112. break;
  113. case 667:
  114. dram_pll_init(MHZ(167));
  115. dram_disable_bypass();
  116. break;
  117. case 400:
  118. dram_enable_bypass(MHZ(400));
  119. break;
  120. case 100:
  121. dram_enable_bypass(MHZ(100));
  122. break;
  123. default:
  124. return;
  125. }
  126. }
  127. void ddrphy_init_read_msg_block(enum fw_type type)
  128. {
  129. }
  130. void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
  131. unsigned int mr_data)
  132. {
  133. unsigned int tmp;
  134. /*
  135. * 1. Poll MRSTAT.mr_wr_busy until it is 0.
  136. * This checks that there is no outstanding MR transaction.
  137. * No writes should be performed to MRCTRL0 and MRCTRL1 if
  138. * MRSTAT.mr_wr_busy = 1.
  139. */
  140. do {
  141. tmp = reg32_read(DDRC_MRSTAT(0));
  142. } while (tmp & 0x1);
  143. /*
  144. * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
  145. * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
  146. */
  147. reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
  148. reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
  149. reg32setbit(DDRC_MRCTRL0(0), 31);
  150. }
  151. unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
  152. {
  153. unsigned int tmp;
  154. reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
  155. do {
  156. tmp = reg32_read(DDRC_MRSTAT(0));
  157. } while (tmp & 0x1);
  158. reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
  159. reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
  160. reg32setbit(DDRC_MRCTRL0(0), 31);
  161. do {
  162. tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
  163. } while ((tmp & 0x8) == 0);
  164. tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
  165. tmp = tmp & 0xff;
  166. reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
  167. return tmp;
  168. }
  169. unsigned int look_for_max(unsigned int data[],
  170. unsigned int addr_start, unsigned int addr_end)
  171. {
  172. unsigned int i, imax = 0;
  173. for (i = addr_start; i <= addr_end; i++) {
  174. if (((data[i] >> 7) == 0) && (data[i] > imax))
  175. imax = data[i];
  176. }
  177. return imax;
  178. }
  179. void get_trained_CDD(u32 fsp)
  180. {
  181. unsigned int i, ddr_type, tmp;
  182. unsigned int cdd_cha[12], cdd_chb[12];
  183. unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
  184. unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
  185. ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
  186. if (ddr_type == 0x20) {
  187. for (i = 0; i < 6; i++) {
  188. tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
  189. cdd_cha[i * 2] = tmp & 0xff;
  190. cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
  191. }
  192. for (i = 0; i < 7; i++) {
  193. tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
  194. if (i == 0) {
  195. cdd_cha[0] = (tmp >> 8) & 0xff;
  196. } else if (i == 6) {
  197. cdd_cha[11] = tmp & 0xff;
  198. } else {
  199. cdd_chb[i * 2 - 1] = tmp & 0xff;
  200. cdd_chb[i * 2] = (tmp >> 8) & 0xff;
  201. }
  202. }
  203. cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
  204. cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
  205. cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
  206. cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
  207. cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
  208. cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
  209. cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
  210. cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
  211. g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
  212. g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
  213. g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
  214. g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
  215. } else {
  216. unsigned int ddr4_cdd[64];
  217. for (i = 0; i < 29; i++) {
  218. tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
  219. ddr4_cdd[i * 2] = tmp & 0xff;
  220. ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
  221. }
  222. g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
  223. g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
  224. g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
  225. g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
  226. }
  227. }
  228. void update_umctl2_rank_space_setting(unsigned int pstat_num)
  229. {
  230. unsigned int i, ddr_type;
  231. unsigned int addr_slot, rdata, tmp, tmp_t;
  232. unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
  233. ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
  234. for (i = 0; i < pstat_num; i++) {
  235. addr_slot = i ? (i + 1) * 0x1000 : 0;
  236. if (ddr_type == 0x20) {
  237. /* update r2w:[13:8], w2r:[5:0] */
  238. rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
  239. ddrc_w2r = rdata & 0x3f;
  240. if (is_imx8mp())
  241. tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
  242. else
  243. tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
  244. ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
  245. ddrc_r2w = (rdata >> 8) & 0x3f;
  246. if (is_imx8mp())
  247. tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
  248. else
  249. tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
  250. ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
  251. tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
  252. reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
  253. } else {
  254. /* update w2r:[5:0] */
  255. rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
  256. ddrc_w2r = rdata & 0x3f;
  257. if (is_imx8mp())
  258. tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
  259. else
  260. tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
  261. ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
  262. tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
  263. reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
  264. /* update r2w:[13:8] */
  265. rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
  266. ddrc_r2w = (rdata >> 8) & 0x3f;
  267. if (is_imx8mp())
  268. tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
  269. else
  270. tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
  271. ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
  272. tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
  273. reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
  274. }
  275. if (!is_imx8mq()) {
  276. /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
  277. rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
  278. ddrc_wr_gap = (rdata >> 8) & 0xf;
  279. if (is_imx8mp())
  280. tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
  281. else
  282. tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
  283. ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
  284. ddrc_rd_gap = (rdata >> 4) & 0xf;
  285. if (is_imx8mp())
  286. tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
  287. else
  288. tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
  289. ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
  290. tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
  291. reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
  292. }
  293. }
  294. if (is_imx8mq()) {
  295. /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
  296. rdata = reg32_read(DDRC_RANKCTL(0));
  297. ddrc_wr_gap = (rdata >> 8) & 0xf;
  298. tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
  299. ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
  300. ddrc_rd_gap = (rdata >> 4) & 0xf;
  301. tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
  302. ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
  303. tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
  304. reg32_write(DDRC_RANKCTL(0), tmp_t);
  305. }
  306. }