core.h 31 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /**
  3. * core.h - DesignWare USB3 DRD Core Header
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported
  11. * to uboot.
  12. *
  13. * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable
  14. *
  15. */
  16. #ifndef __DRIVERS_USB_DWC3_CORE_H
  17. #define __DRIVERS_USB_DWC3_CORE_H
  18. #include <linux/ioport.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/otg.h>
  21. #define DWC3_MSG_MAX 500
  22. /* Global constants */
  23. #define DWC3_EP0_BOUNCE_SIZE 512
  24. #define DWC3_ENDPOINTS_NUM 32
  25. #define DWC3_XHCI_RESOURCES_NUM 2
  26. #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
  27. #define DWC3_EVENT_SIZE 4 /* bytes */
  28. #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
  29. #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
  30. #define DWC3_EVENT_TYPE_MASK 0xfe
  31. #define DWC3_EVENT_TYPE_DEV 0
  32. #define DWC3_EVENT_TYPE_CARKIT 3
  33. #define DWC3_EVENT_TYPE_I2C 4
  34. #define DWC3_DEVICE_EVENT_DISCONNECT 0
  35. #define DWC3_DEVICE_EVENT_RESET 1
  36. #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
  37. #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
  38. #define DWC3_DEVICE_EVENT_WAKEUP 4
  39. #define DWC3_DEVICE_EVENT_HIBER_REQ 5
  40. #define DWC3_DEVICE_EVENT_EOPF 6
  41. #define DWC3_DEVICE_EVENT_SOF 7
  42. #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
  43. #define DWC3_DEVICE_EVENT_CMD_CMPL 10
  44. #define DWC3_DEVICE_EVENT_OVERFLOW 11
  45. #define DWC3_GEVNTCOUNT_MASK 0xfffc
  46. #define DWC3_GSNPSID_MASK 0xffff0000
  47. #define DWC3_GSNPSREV_MASK 0xffff
  48. /* DWC3 registers memory space boundries */
  49. #define DWC3_XHCI_REGS_START 0x0
  50. #define DWC3_XHCI_REGS_END 0x7fff
  51. #define DWC3_GLOBALS_REGS_START 0xc100
  52. #define DWC3_GLOBALS_REGS_END 0xc6ff
  53. #define DWC3_DEVICE_REGS_START 0xc700
  54. #define DWC3_DEVICE_REGS_END 0xcbff
  55. #define DWC3_OTG_REGS_START 0xcc00
  56. #define DWC3_OTG_REGS_END 0xccff
  57. /* Global Registers */
  58. #define DWC3_GSBUSCFG0 0xc100
  59. #define DWC3_GSBUSCFG1 0xc104
  60. #define DWC3_GTXTHRCFG 0xc108
  61. #define DWC3_GRXTHRCFG 0xc10c
  62. #define DWC3_GCTL 0xc110
  63. #define DWC3_GEVTEN 0xc114
  64. #define DWC3_GSTS 0xc118
  65. #define DWC3_GSNPSID 0xc120
  66. #define DWC3_GGPIO 0xc124
  67. #define DWC3_GUID 0xc128
  68. #define DWC3_GUCTL 0xc12c
  69. #define DWC3_GBUSERRADDR0 0xc130
  70. #define DWC3_GBUSERRADDR1 0xc134
  71. #define DWC3_GPRTBIMAP0 0xc138
  72. #define DWC3_GPRTBIMAP1 0xc13c
  73. #define DWC3_GHWPARAMS0 0xc140
  74. #define DWC3_GHWPARAMS1 0xc144
  75. #define DWC3_GHWPARAMS2 0xc148
  76. #define DWC3_GHWPARAMS3 0xc14c
  77. #define DWC3_GHWPARAMS4 0xc150
  78. #define DWC3_GHWPARAMS5 0xc154
  79. #define DWC3_GHWPARAMS6 0xc158
  80. #define DWC3_GHWPARAMS7 0xc15c
  81. #define DWC3_GDBGFIFOSPACE 0xc160
  82. #define DWC3_GDBGLTSSM 0xc164
  83. #define DWC3_GPRTBIMAP_HS0 0xc180
  84. #define DWC3_GPRTBIMAP_HS1 0xc184
  85. #define DWC3_GPRTBIMAP_FS0 0xc188
  86. #define DWC3_GPRTBIMAP_FS1 0xc18c
  87. #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
  88. #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
  89. #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
  90. #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
  91. #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
  92. #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
  93. #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
  94. #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
  95. #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
  96. #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
  97. #define DWC3_GHWPARAMS8 0xc600
  98. /* Device Registers */
  99. #define DWC3_DCFG 0xc700
  100. #define DWC3_DCTL 0xc704
  101. #define DWC3_DEVTEN 0xc708
  102. #define DWC3_DSTS 0xc70c
  103. #define DWC3_DGCMDPAR 0xc710
  104. #define DWC3_DGCMD 0xc714
  105. #define DWC3_DALEPENA 0xc720
  106. #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
  107. #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
  108. #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
  109. #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
  110. /* OTG Registers */
  111. #define DWC3_OCFG 0xcc00
  112. #define DWC3_OCTL 0xcc04
  113. #define DWC3_OEVT 0xcc08
  114. #define DWC3_OEVTEN 0xcc0C
  115. #define DWC3_OSTS 0xcc10
  116. /* Bit fields */
  117. /* Global Configuration Register */
  118. #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
  119. #define DWC3_GCTL_U2RSTECN (1 << 16)
  120. #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
  121. #define DWC3_GCTL_CLK_BUS (0)
  122. #define DWC3_GCTL_CLK_PIPE (1)
  123. #define DWC3_GCTL_CLK_PIPEHALF (2)
  124. #define DWC3_GCTL_CLK_MASK (3)
  125. #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
  126. #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
  127. #define DWC3_GCTL_PRTCAP_HOST 1
  128. #define DWC3_GCTL_PRTCAP_DEVICE 2
  129. #define DWC3_GCTL_PRTCAP_OTG 3
  130. #define DWC3_GCTL_CORESOFTRESET (1 << 11)
  131. #define DWC3_GCTL_SOFITPSYNC (1 << 10)
  132. #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
  133. #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
  134. #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
  135. #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
  136. #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
  137. #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
  138. /* Global USB2 PHY Configuration Register */
  139. #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
  140. #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
  141. #define DWC3_GUSB2PHYCFG_PHYIF BIT(3)
  142. /* Global USB2 PHY Configuration Mask */
  143. #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
  144. /* Global USB2 PHY Configuration Offset */
  145. #define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
  146. #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
  147. DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
  148. #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
  149. DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
  150. /* Global USB3 PIPE Control Register */
  151. #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
  152. #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
  153. #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
  154. #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
  155. #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
  156. #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
  157. #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
  158. #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
  159. #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
  160. #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
  161. #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
  162. #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
  163. /* Global TX Fifo Size Register */
  164. #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
  165. #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
  166. /* Global Event Size Registers */
  167. #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
  168. #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
  169. /* Global HWPARAMS1 Register */
  170. #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
  171. #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
  172. #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
  173. #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
  174. #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
  175. #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
  176. /* Global HWPARAMS3 Register */
  177. #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
  178. #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
  179. #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
  180. #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
  181. #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
  182. #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
  183. #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
  184. #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
  185. #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
  186. #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
  187. #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
  188. /* Global HWPARAMS4 Register */
  189. #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
  190. #define DWC3_MAX_HIBER_SCRATCHBUFS 15
  191. /* Global HWPARAMS6 Register */
  192. #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
  193. /* Device Configuration Register */
  194. #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
  195. #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
  196. #define DWC3_DCFG_SPEED_MASK (7 << 0)
  197. #define DWC3_DCFG_SUPERSPEED (4 << 0)
  198. #define DWC3_DCFG_HIGHSPEED (0 << 0)
  199. #define DWC3_DCFG_FULLSPEED2 (1 << 0)
  200. #define DWC3_DCFG_LOWSPEED (2 << 0)
  201. #define DWC3_DCFG_FULLSPEED1 (3 << 0)
  202. #define DWC3_DCFG_LPM_CAP (1 << 22)
  203. /* Device Control Register */
  204. #define DWC3_DCTL_RUN_STOP (1 << 31)
  205. #define DWC3_DCTL_CSFTRST (1 << 30)
  206. #define DWC3_DCTL_LSFTRST (1 << 29)
  207. #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
  208. #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
  209. #define DWC3_DCTL_APPL1RES (1 << 23)
  210. /* These apply for core versions 1.87a and earlier */
  211. #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
  212. #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
  213. #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
  214. #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
  215. #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
  216. #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
  217. #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
  218. /* These apply for core versions 1.94a and later */
  219. #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
  220. #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
  221. #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
  222. #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
  223. #define DWC3_DCTL_CRS (1 << 17)
  224. #define DWC3_DCTL_CSS (1 << 16)
  225. #define DWC3_DCTL_INITU2ENA (1 << 12)
  226. #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
  227. #define DWC3_DCTL_INITU1ENA (1 << 10)
  228. #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
  229. #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
  230. #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
  231. #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
  232. #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
  233. #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
  234. #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
  235. #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
  236. #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
  237. #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
  238. #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
  239. /* Device Event Enable Register */
  240. #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
  241. #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
  242. #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
  243. #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
  244. #define DWC3_DEVTEN_SOFEN (1 << 7)
  245. #define DWC3_DEVTEN_EOPFEN (1 << 6)
  246. #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
  247. #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
  248. #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
  249. #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
  250. #define DWC3_DEVTEN_USBRSTEN (1 << 1)
  251. #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
  252. /* Device Status Register */
  253. #define DWC3_DSTS_DCNRD (1 << 29)
  254. /* This applies for core versions 1.87a and earlier */
  255. #define DWC3_DSTS_PWRUPREQ (1 << 24)
  256. /* These apply for core versions 1.94a and later */
  257. #define DWC3_DSTS_RSS (1 << 25)
  258. #define DWC3_DSTS_SSS (1 << 24)
  259. #define DWC3_DSTS_COREIDLE (1 << 23)
  260. #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
  261. #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
  262. #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
  263. #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
  264. #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
  265. #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
  266. #define DWC3_DSTS_CONNECTSPD (7 << 0)
  267. #define DWC3_DSTS_SUPERSPEED (4 << 0)
  268. #define DWC3_DSTS_HIGHSPEED (0 << 0)
  269. #define DWC3_DSTS_FULLSPEED2 (1 << 0)
  270. #define DWC3_DSTS_LOWSPEED (2 << 0)
  271. #define DWC3_DSTS_FULLSPEED1 (3 << 0)
  272. /* Device Generic Command Register */
  273. #define DWC3_DGCMD_SET_LMP 0x01
  274. #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
  275. #define DWC3_DGCMD_XMIT_FUNCTION 0x03
  276. /* These apply for core versions 1.94a and later */
  277. #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
  278. #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
  279. #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
  280. #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
  281. #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
  282. #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
  283. #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
  284. #define DWC3_DGCMD_CMDACT (1 << 10)
  285. #define DWC3_DGCMD_CMDIOC (1 << 8)
  286. /* Device Generic Command Parameter Register */
  287. #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
  288. #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
  289. #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
  290. #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
  291. #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
  292. #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
  293. /* Device Endpoint Command Register */
  294. #define DWC3_DEPCMD_PARAM_SHIFT 16
  295. #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
  296. #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
  297. #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
  298. #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
  299. #define DWC3_DEPCMD_CMDACT (1 << 10)
  300. #define DWC3_DEPCMD_CMDIOC (1 << 8)
  301. #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
  302. #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
  303. #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
  304. #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
  305. #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
  306. #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
  307. /* This applies for core versions 1.90a and earlier */
  308. #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
  309. /* This applies for core versions 1.94a and later */
  310. #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
  311. #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
  312. #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
  313. /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
  314. #define DWC3_DALEPENA_EP(n) (1 << n)
  315. #define DWC3_DEPCMD_TYPE_CONTROL 0
  316. #define DWC3_DEPCMD_TYPE_ISOC 1
  317. #define DWC3_DEPCMD_TYPE_BULK 2
  318. #define DWC3_DEPCMD_TYPE_INTR 3
  319. /* Structures */
  320. struct dwc3_trb;
  321. /**
  322. * struct dwc3_event_buffer - Software event buffer representation
  323. * @buf: _THE_ buffer
  324. * @length: size of this buffer
  325. * @lpos: event offset
  326. * @count: cache of last read event count register
  327. * @flags: flags related to this event buffer
  328. * @dma: dma_addr_t
  329. * @dwc: pointer to DWC controller
  330. */
  331. struct dwc3_event_buffer {
  332. void *buf;
  333. unsigned length;
  334. unsigned int lpos;
  335. unsigned int count;
  336. unsigned int flags;
  337. #define DWC3_EVENT_PENDING (1UL << 0)
  338. dma_addr_t dma;
  339. struct dwc3 *dwc;
  340. };
  341. #define DWC3_EP_FLAG_STALLED (1 << 0)
  342. #define DWC3_EP_FLAG_WEDGED (1 << 1)
  343. #define DWC3_EP_DIRECTION_TX true
  344. #define DWC3_EP_DIRECTION_RX false
  345. #define DWC3_TRB_NUM 32
  346. #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
  347. /**
  348. * struct dwc3_ep - device side endpoint representation
  349. * @endpoint: usb endpoint
  350. * @request_list: list of requests for this endpoint
  351. * @req_queued: list of requests on this ep which have TRBs setup
  352. * @trb_pool: array of transaction buffers
  353. * @trb_pool_dma: dma address of @trb_pool
  354. * @free_slot: next slot which is going to be used
  355. * @busy_slot: first slot which is owned by HW
  356. * @desc: usb_endpoint_descriptor pointer
  357. * @dwc: pointer to DWC controller
  358. * @saved_state: ep state saved during hibernation
  359. * @flags: endpoint flags (wedged, stalled, ...)
  360. * @current_trb: index of current used trb
  361. * @number: endpoint number (1 - 15)
  362. * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
  363. * @resource_index: Resource transfer index
  364. * @interval: the interval on which the ISOC transfer is started
  365. * @name: a human readable name e.g. ep1out-bulk
  366. * @direction: true for TX, false for RX
  367. * @stream_capable: true when streams are enabled
  368. */
  369. struct dwc3_ep {
  370. struct usb_ep endpoint;
  371. struct list_head request_list;
  372. struct list_head req_queued;
  373. struct dwc3_trb *trb_pool;
  374. dma_addr_t trb_pool_dma;
  375. u32 free_slot;
  376. u32 busy_slot;
  377. const struct usb_ss_ep_comp_descriptor *comp_desc;
  378. struct dwc3 *dwc;
  379. u32 saved_state;
  380. unsigned flags;
  381. #define DWC3_EP_ENABLED (1 << 0)
  382. #define DWC3_EP_STALL (1 << 1)
  383. #define DWC3_EP_WEDGE (1 << 2)
  384. #define DWC3_EP_BUSY (1 << 4)
  385. #define DWC3_EP_PENDING_REQUEST (1 << 5)
  386. #define DWC3_EP_MISSED_ISOC (1 << 6)
  387. /* This last one is specific to EP0 */
  388. #define DWC3_EP0_DIR_IN (1 << 31)
  389. unsigned current_trb;
  390. u8 number;
  391. u8 type;
  392. u8 resource_index;
  393. u32 interval;
  394. char name[20];
  395. unsigned direction:1;
  396. unsigned stream_capable:1;
  397. };
  398. enum dwc3_phy {
  399. DWC3_PHY_UNKNOWN = 0,
  400. DWC3_PHY_USB3,
  401. DWC3_PHY_USB2,
  402. };
  403. enum dwc3_ep0_next {
  404. DWC3_EP0_UNKNOWN = 0,
  405. DWC3_EP0_COMPLETE,
  406. DWC3_EP0_NRDY_DATA,
  407. DWC3_EP0_NRDY_STATUS,
  408. };
  409. enum dwc3_ep0_state {
  410. EP0_UNCONNECTED = 0,
  411. EP0_SETUP_PHASE,
  412. EP0_DATA_PHASE,
  413. EP0_STATUS_PHASE,
  414. };
  415. enum dwc3_link_state {
  416. /* In SuperSpeed */
  417. DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
  418. DWC3_LINK_STATE_U1 = 0x01,
  419. DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
  420. DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
  421. DWC3_LINK_STATE_SS_DIS = 0x04,
  422. DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
  423. DWC3_LINK_STATE_SS_INACT = 0x06,
  424. DWC3_LINK_STATE_POLL = 0x07,
  425. DWC3_LINK_STATE_RECOV = 0x08,
  426. DWC3_LINK_STATE_HRESET = 0x09,
  427. DWC3_LINK_STATE_CMPLY = 0x0a,
  428. DWC3_LINK_STATE_LPBK = 0x0b,
  429. DWC3_LINK_STATE_RESET = 0x0e,
  430. DWC3_LINK_STATE_RESUME = 0x0f,
  431. DWC3_LINK_STATE_MASK = 0x0f,
  432. };
  433. /* TRB Length, PCM and Status */
  434. #define DWC3_TRB_SIZE_MASK (0x00ffffff)
  435. #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
  436. #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
  437. #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
  438. #define DWC3_TRBSTS_OK 0
  439. #define DWC3_TRBSTS_MISSED_ISOC 1
  440. #define DWC3_TRBSTS_SETUP_PENDING 2
  441. #define DWC3_TRB_STS_XFER_IN_PROG 4
  442. /* TRB Control */
  443. #define DWC3_TRB_CTRL_HWO (1 << 0)
  444. #define DWC3_TRB_CTRL_LST (1 << 1)
  445. #define DWC3_TRB_CTRL_CHN (1 << 2)
  446. #define DWC3_TRB_CTRL_CSP (1 << 3)
  447. #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
  448. #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
  449. #define DWC3_TRB_CTRL_IOC (1 << 11)
  450. #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
  451. #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
  452. #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
  453. #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
  454. #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
  455. #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
  456. #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
  457. #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
  458. #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
  459. /**
  460. * struct dwc3_trb - transfer request block (hw format)
  461. * @bpl: DW0-3
  462. * @bph: DW4-7
  463. * @size: DW8-B
  464. * @trl: DWC-F
  465. */
  466. struct dwc3_trb {
  467. u32 bpl;
  468. u32 bph;
  469. u32 size;
  470. u32 ctrl;
  471. } __packed;
  472. /**
  473. * dwc3_hwparams - copy of HWPARAMS registers
  474. * @hwparams0 - GHWPARAMS0
  475. * @hwparams1 - GHWPARAMS1
  476. * @hwparams2 - GHWPARAMS2
  477. * @hwparams3 - GHWPARAMS3
  478. * @hwparams4 - GHWPARAMS4
  479. * @hwparams5 - GHWPARAMS5
  480. * @hwparams6 - GHWPARAMS6
  481. * @hwparams7 - GHWPARAMS7
  482. * @hwparams8 - GHWPARAMS8
  483. */
  484. struct dwc3_hwparams {
  485. u32 hwparams0;
  486. u32 hwparams1;
  487. u32 hwparams2;
  488. u32 hwparams3;
  489. u32 hwparams4;
  490. u32 hwparams5;
  491. u32 hwparams6;
  492. u32 hwparams7;
  493. u32 hwparams8;
  494. };
  495. /* HWPARAMS0 */
  496. #define DWC3_MODE(n) ((n) & 0x7)
  497. #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
  498. /* HWPARAMS1 */
  499. #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
  500. /* HWPARAMS3 */
  501. #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
  502. #define DWC3_NUM_EPS_MASK (0x3f << 12)
  503. #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
  504. (DWC3_NUM_EPS_MASK)) >> 12)
  505. #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
  506. (DWC3_NUM_IN_EPS_MASK)) >> 18)
  507. /* HWPARAMS7 */
  508. #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
  509. struct dwc3_request {
  510. struct usb_request request;
  511. struct list_head list;
  512. struct dwc3_ep *dep;
  513. u32 start_slot;
  514. u8 epnum;
  515. struct dwc3_trb *trb;
  516. dma_addr_t trb_dma;
  517. unsigned direction:1;
  518. unsigned mapped:1;
  519. unsigned queued:1;
  520. };
  521. /*
  522. * struct dwc3_scratchpad_array - hibernation scratchpad array
  523. * (format defined by hw)
  524. */
  525. struct dwc3_scratchpad_array {
  526. __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
  527. };
  528. /**
  529. * struct dwc3 - representation of our controller
  530. * @ctrl_req: usb control request which is used for ep0
  531. * @ep0_trb: trb which is used for the ctrl_req
  532. * @ep0_bounce: bounce buffer for ep0
  533. * @setup_buf: used while precessing STD USB requests
  534. * @ctrl_req_addr: dma address of ctrl_req
  535. * @ep0_trb: dma address of ep0_trb
  536. * @ep0_usb_req: dummy req used while handling STD USB requests
  537. * @ep0_bounce_addr: dma address of ep0_bounce
  538. * @scratch_addr: dma address of scratchbuf
  539. * @lock: for synchronizing
  540. * @dev: pointer to our struct device
  541. * @xhci: pointer to our xHCI child
  542. * @event_buffer_list: a list of event buffers
  543. * @gadget: device side representation of the peripheral controller
  544. * @gadget_driver: pointer to the gadget driver
  545. * @regs: base address for our registers
  546. * @regs_size: address space size
  547. * @nr_scratch: number of scratch buffers
  548. * @num_event_buffers: calculated number of event buffers
  549. * @u1u2: only used on revisions <1.83a for workaround
  550. * @maximum_speed: maximum speed requested (mainly for testing purposes)
  551. * @revision: revision register contents
  552. * @dr_mode: requested mode of operation
  553. * @dcfg: saved contents of DCFG register
  554. * @gctl: saved contents of GCTL register
  555. * @isoch_delay: wValue from Set Isochronous Delay request;
  556. * @u2sel: parameter from Set SEL request.
  557. * @u2pel: parameter from Set SEL request.
  558. * @u1sel: parameter from Set SEL request.
  559. * @u1pel: parameter from Set SEL request.
  560. * @num_out_eps: number of out endpoints
  561. * @num_in_eps: number of in endpoints
  562. * @ep0_next_event: hold the next expected event
  563. * @ep0state: state of endpoint zero
  564. * @link_state: link state
  565. * @speed: device speed (super, high, full, low)
  566. * @mem: points to start of memory which is used for this struct.
  567. * @hwparams: copy of hwparams registers
  568. * @root: debugfs root folder pointer
  569. * @regset: debugfs pointer to regdump file
  570. * @test_mode: true when we're entering a USB test mode
  571. * @test_mode_nr: test feature selector
  572. * @lpm_nyet_threshold: LPM NYET response threshold
  573. * @hird_threshold: HIRD threshold
  574. * @delayed_status: true when gadget driver asks for delayed status
  575. * @ep0_bounced: true when we used bounce buffer
  576. * @ep0_expect_in: true when we expect a DATA IN transfer
  577. * @has_hibernation: true when dwc3 was configured with Hibernation
  578. * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
  579. * there's now way for software to detect this in runtime.
  580. * @is_utmi_l1_suspend: the core asserts output signal
  581. * 0 - utmi_sleep_n
  582. * 1 - utmi_l1_suspend_n
  583. * @is_selfpowered: true when we are selfpowered
  584. * @is_fpga: true when we are using the FPGA board
  585. * @needs_fifo_resize: not all users might want fifo resizing, flag it
  586. * @pullups_connected: true when Run/Stop bit is set
  587. * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
  588. * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
  589. * @start_config_issued: true when StartConfig command has been issued
  590. * @three_stage_setup: set if we perform a three phase setup
  591. * @disable_scramble_quirk: set if we enable the disable scramble quirk
  592. * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
  593. * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
  594. * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
  595. * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
  596. * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
  597. * @lfps_filter_quirk: set if we enable LFPS filter quirk
  598. * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
  599. * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
  600. * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
  601. * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  602. * @tx_de_emphasis: Tx de-emphasis value
  603. * 0 - -6dB de-emphasis
  604. * 1 - -3.5dB de-emphasis
  605. * 2 - No de-emphasis
  606. * 3 - Reserved
  607. * @index: index of _this_ controller
  608. * @list: to maintain the list of dwc3 controllers
  609. */
  610. struct dwc3 {
  611. struct usb_ctrlrequest *ctrl_req;
  612. struct dwc3_trb *ep0_trb;
  613. void *ep0_bounce;
  614. void *scratchbuf;
  615. u8 *setup_buf;
  616. dma_addr_t ctrl_req_addr;
  617. dma_addr_t ep0_trb_addr;
  618. dma_addr_t ep0_bounce_addr;
  619. dma_addr_t scratch_addr;
  620. struct dwc3_request ep0_usb_req;
  621. /* device lock */
  622. spinlock_t lock;
  623. #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB)
  624. struct udevice *dev;
  625. #else
  626. struct device *dev;
  627. #endif
  628. struct platform_device *xhci;
  629. struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
  630. struct dwc3_event_buffer **ev_buffs;
  631. struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
  632. struct usb_gadget gadget;
  633. struct usb_gadget_driver *gadget_driver;
  634. void __iomem *regs;
  635. size_t regs_size;
  636. enum usb_dr_mode dr_mode;
  637. /* used for suspend/resume */
  638. u32 dcfg;
  639. u32 gctl;
  640. u32 nr_scratch;
  641. u32 num_event_buffers;
  642. u32 u1u2;
  643. u32 maximum_speed;
  644. u32 revision;
  645. #define DWC3_REVISION_173A 0x5533173a
  646. #define DWC3_REVISION_175A 0x5533175a
  647. #define DWC3_REVISION_180A 0x5533180a
  648. #define DWC3_REVISION_183A 0x5533183a
  649. #define DWC3_REVISION_185A 0x5533185a
  650. #define DWC3_REVISION_187A 0x5533187a
  651. #define DWC3_REVISION_188A 0x5533188a
  652. #define DWC3_REVISION_190A 0x5533190a
  653. #define DWC3_REVISION_194A 0x5533194a
  654. #define DWC3_REVISION_200A 0x5533200a
  655. #define DWC3_REVISION_202A 0x5533202a
  656. #define DWC3_REVISION_210A 0x5533210a
  657. #define DWC3_REVISION_220A 0x5533220a
  658. #define DWC3_REVISION_230A 0x5533230a
  659. #define DWC3_REVISION_240A 0x5533240a
  660. #define DWC3_REVISION_250A 0x5533250a
  661. #define DWC3_REVISION_260A 0x5533260a
  662. #define DWC3_REVISION_270A 0x5533270a
  663. #define DWC3_REVISION_280A 0x5533280a
  664. enum dwc3_ep0_next ep0_next_event;
  665. enum dwc3_ep0_state ep0state;
  666. enum dwc3_link_state link_state;
  667. u16 isoch_delay;
  668. u16 u2sel;
  669. u16 u2pel;
  670. u8 u1sel;
  671. u8 u1pel;
  672. u8 speed;
  673. u8 num_out_eps;
  674. u8 num_in_eps;
  675. void *mem;
  676. struct dwc3_hwparams hwparams;
  677. struct dentry *root;
  678. struct debugfs_regset32 *regset;
  679. u8 test_mode;
  680. u8 test_mode_nr;
  681. u8 lpm_nyet_threshold;
  682. u8 hird_threshold;
  683. unsigned delayed_status:1;
  684. unsigned ep0_bounced:1;
  685. unsigned ep0_expect_in:1;
  686. unsigned has_hibernation:1;
  687. unsigned has_lpm_erratum:1;
  688. unsigned is_utmi_l1_suspend:1;
  689. unsigned is_selfpowered:1;
  690. unsigned is_fpga:1;
  691. unsigned needs_fifo_resize:1;
  692. unsigned pullups_connected:1;
  693. unsigned resize_fifos:1;
  694. unsigned setup_packet_pending:1;
  695. unsigned start_config_issued:1;
  696. unsigned three_stage_setup:1;
  697. unsigned disable_scramble_quirk:1;
  698. unsigned u2exit_lfps_quirk:1;
  699. unsigned u2ss_inp3_quirk:1;
  700. unsigned req_p1p2p3_quirk:1;
  701. unsigned del_p1p2p3_quirk:1;
  702. unsigned del_phy_power_chg_quirk:1;
  703. unsigned lfps_filter_quirk:1;
  704. unsigned rx_detect_poll_quirk:1;
  705. unsigned dis_u3_susphy_quirk:1;
  706. unsigned dis_u2_susphy_quirk:1;
  707. unsigned tx_de_emphasis_quirk:1;
  708. unsigned tx_de_emphasis:2;
  709. int index;
  710. struct list_head list;
  711. };
  712. /* -------------------------------------------------------------------------- */
  713. /* -------------------------------------------------------------------------- */
  714. struct dwc3_event_type {
  715. u32 is_devspec:1;
  716. u32 type:7;
  717. u32 reserved8_31:24;
  718. } __packed;
  719. #define DWC3_DEPEVT_XFERCOMPLETE 0x01
  720. #define DWC3_DEPEVT_XFERINPROGRESS 0x02
  721. #define DWC3_DEPEVT_XFERNOTREADY 0x03
  722. #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
  723. #define DWC3_DEPEVT_STREAMEVT 0x06
  724. #define DWC3_DEPEVT_EPCMDCMPLT 0x07
  725. /**
  726. * dwc3_ep_event_string - returns event name
  727. * @event: then event code
  728. */
  729. static inline const char *dwc3_ep_event_string(u8 event)
  730. {
  731. switch (event) {
  732. case DWC3_DEPEVT_XFERCOMPLETE:
  733. return "Transfer Complete";
  734. case DWC3_DEPEVT_XFERINPROGRESS:
  735. return "Transfer In-Progress";
  736. case DWC3_DEPEVT_XFERNOTREADY:
  737. return "Transfer Not Ready";
  738. case DWC3_DEPEVT_RXTXFIFOEVT:
  739. return "FIFO";
  740. case DWC3_DEPEVT_STREAMEVT:
  741. return "Stream";
  742. case DWC3_DEPEVT_EPCMDCMPLT:
  743. return "Endpoint Command Complete";
  744. }
  745. return "UNKNOWN";
  746. }
  747. /**
  748. * struct dwc3_event_depvt - Device Endpoint Events
  749. * @one_bit: indicates this is an endpoint event (not used)
  750. * @endpoint_number: number of the endpoint
  751. * @endpoint_event: The event we have:
  752. * 0x00 - Reserved
  753. * 0x01 - XferComplete
  754. * 0x02 - XferInProgress
  755. * 0x03 - XferNotReady
  756. * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
  757. * 0x05 - Reserved
  758. * 0x06 - StreamEvt
  759. * 0x07 - EPCmdCmplt
  760. * @reserved11_10: Reserved, don't use.
  761. * @status: Indicates the status of the event. Refer to databook for
  762. * more information.
  763. * @parameters: Parameters of the current event. Refer to databook for
  764. * more information.
  765. */
  766. struct dwc3_event_depevt {
  767. u32 one_bit:1;
  768. u32 endpoint_number:5;
  769. u32 endpoint_event:4;
  770. u32 reserved11_10:2;
  771. u32 status:4;
  772. /* Within XferNotReady */
  773. #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
  774. /* Within XferComplete */
  775. #define DEPEVT_STATUS_BUSERR (1 << 0)
  776. #define DEPEVT_STATUS_SHORT (1 << 1)
  777. #define DEPEVT_STATUS_IOC (1 << 2)
  778. #define DEPEVT_STATUS_LST (1 << 3)
  779. /* Stream event only */
  780. #define DEPEVT_STREAMEVT_FOUND 1
  781. #define DEPEVT_STREAMEVT_NOTFOUND 2
  782. /* Control-only Status */
  783. #define DEPEVT_STATUS_CONTROL_DATA 1
  784. #define DEPEVT_STATUS_CONTROL_STATUS 2
  785. u32 parameters:16;
  786. } __packed;
  787. /**
  788. * struct dwc3_event_devt - Device Events
  789. * @one_bit: indicates this is a non-endpoint event (not used)
  790. * @device_event: indicates it's a device event. Should read as 0x00
  791. * @type: indicates the type of device event.
  792. * 0 - DisconnEvt
  793. * 1 - USBRst
  794. * 2 - ConnectDone
  795. * 3 - ULStChng
  796. * 4 - WkUpEvt
  797. * 5 - Reserved
  798. * 6 - EOPF
  799. * 7 - SOF
  800. * 8 - Reserved
  801. * 9 - ErrticErr
  802. * 10 - CmdCmplt
  803. * 11 - EvntOverflow
  804. * 12 - VndrDevTstRcved
  805. * @reserved15_12: Reserved, not used
  806. * @event_info: Information about this event
  807. * @reserved31_25: Reserved, not used
  808. */
  809. struct dwc3_event_devt {
  810. u32 one_bit:1;
  811. u32 device_event:7;
  812. u32 type:4;
  813. u32 reserved15_12:4;
  814. u32 event_info:9;
  815. u32 reserved31_25:7;
  816. } __packed;
  817. /**
  818. * struct dwc3_event_gevt - Other Core Events
  819. * @one_bit: indicates this is a non-endpoint event (not used)
  820. * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
  821. * @phy_port_number: self-explanatory
  822. * @reserved31_12: Reserved, not used.
  823. */
  824. struct dwc3_event_gevt {
  825. u32 one_bit:1;
  826. u32 device_event:7;
  827. u32 phy_port_number:4;
  828. u32 reserved31_12:20;
  829. } __packed;
  830. /**
  831. * union dwc3_event - representation of Event Buffer contents
  832. * @raw: raw 32-bit event
  833. * @type: the type of the event
  834. * @depevt: Device Endpoint Event
  835. * @devt: Device Event
  836. * @gevt: Global Event
  837. */
  838. union dwc3_event {
  839. u32 raw;
  840. struct dwc3_event_type type;
  841. struct dwc3_event_depevt depevt;
  842. struct dwc3_event_devt devt;
  843. struct dwc3_event_gevt gevt;
  844. };
  845. /**
  846. * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
  847. * parameters
  848. * @param2: third parameter
  849. * @param1: second parameter
  850. * @param0: first parameter
  851. */
  852. struct dwc3_gadget_ep_cmd_params {
  853. u32 param2;
  854. u32 param1;
  855. u32 param0;
  856. };
  857. /*
  858. * DWC3 Features to be used as Driver Data
  859. */
  860. #define DWC3_HAS_PERIPHERAL BIT(0)
  861. #define DWC3_HAS_XHCI BIT(1)
  862. #define DWC3_HAS_OTG BIT(3)
  863. /* prototypes */
  864. int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
  865. void dwc3_of_parse(struct dwc3 *dwc);
  866. int dwc3_init(struct dwc3 *dwc);
  867. void dwc3_remove(struct dwc3 *dwc);
  868. static inline int dwc3_host_init(struct dwc3 *dwc)
  869. { return 0; }
  870. static inline void dwc3_host_exit(struct dwc3 *dwc)
  871. { }
  872. #ifdef CONFIG_USB_DWC3_GADGET
  873. int dwc3_gadget_init(struct dwc3 *dwc);
  874. void dwc3_gadget_exit(struct dwc3 *dwc);
  875. int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
  876. int dwc3_gadget_get_link_state(struct dwc3 *dwc);
  877. int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
  878. int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
  879. unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
  880. int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
  881. #else
  882. static inline int dwc3_gadget_init(struct dwc3 *dwc)
  883. { return 0; }
  884. static inline void dwc3_gadget_exit(struct dwc3 *dwc)
  885. { }
  886. static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  887. { return 0; }
  888. static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  889. { return 0; }
  890. static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
  891. enum dwc3_link_state state)
  892. { return 0; }
  893. static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
  894. unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
  895. { return 0; }
  896. static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
  897. int cmd, u32 param)
  898. { return 0; }
  899. #endif
  900. #endif /* __DRIVERS_USB_DWC3_CORE_H */