core.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * core.c - DesignWare USB3 DRD Controller Core file
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11. * to uboot.
  12. *
  13. * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14. */
  15. #include <common.h>
  16. #include <malloc.h>
  17. #include <dwc3-uboot.h>
  18. #include <asm/dma-mapping.h>
  19. #include <linux/ioport.h>
  20. #include <dm.h>
  21. #include <generic-phy.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/gadget.h>
  24. #include "core.h"
  25. #include "gadget.h"
  26. #include "io.h"
  27. #include "linux-compat.h"
  28. static LIST_HEAD(dwc3_list);
  29. /* -------------------------------------------------------------------------- */
  30. static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  31. {
  32. u32 reg;
  33. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  34. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  35. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  36. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  37. }
  38. /**
  39. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  40. * @dwc: pointer to our context structure
  41. */
  42. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  43. {
  44. u32 reg;
  45. /* Before Resetting PHY, put Core in Reset */
  46. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  47. reg |= DWC3_GCTL_CORESOFTRESET;
  48. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  49. /* Assert USB3 PHY reset */
  50. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  51. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  52. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  53. /* Assert USB2 PHY reset */
  54. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  55. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  56. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  57. mdelay(100);
  58. /* Clear USB3 PHY reset */
  59. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  60. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  61. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  62. /* Clear USB2 PHY reset */
  63. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  64. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  65. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  66. mdelay(100);
  67. /* After PHYs are stable we can take Core out of reset state */
  68. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  69. reg &= ~DWC3_GCTL_CORESOFTRESET;
  70. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  71. return 0;
  72. }
  73. /**
  74. * dwc3_free_one_event_buffer - Frees one event buffer
  75. * @dwc: Pointer to our controller context structure
  76. * @evt: Pointer to event buffer to be freed
  77. */
  78. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  79. struct dwc3_event_buffer *evt)
  80. {
  81. dma_free_coherent(evt->buf);
  82. }
  83. /**
  84. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  85. * @dwc: Pointer to our controller context structure
  86. * @length: size of the event buffer
  87. *
  88. * Returns a pointer to the allocated event buffer structure on success
  89. * otherwise ERR_PTR(errno).
  90. */
  91. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  92. unsigned length)
  93. {
  94. struct dwc3_event_buffer *evt;
  95. evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
  96. GFP_KERNEL);
  97. if (!evt)
  98. return ERR_PTR(-ENOMEM);
  99. evt->dwc = dwc;
  100. evt->length = length;
  101. evt->buf = dma_alloc_coherent(length,
  102. (unsigned long *)&evt->dma);
  103. if (!evt->buf)
  104. return ERR_PTR(-ENOMEM);
  105. dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
  106. return evt;
  107. }
  108. /**
  109. * dwc3_free_event_buffers - frees all allocated event buffers
  110. * @dwc: Pointer to our controller context structure
  111. */
  112. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  113. {
  114. struct dwc3_event_buffer *evt;
  115. int i;
  116. for (i = 0; i < dwc->num_event_buffers; i++) {
  117. evt = dwc->ev_buffs[i];
  118. if (evt)
  119. dwc3_free_one_event_buffer(dwc, evt);
  120. }
  121. }
  122. /**
  123. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  124. * @dwc: pointer to our controller context structure
  125. * @length: size of event buffer
  126. *
  127. * Returns 0 on success otherwise negative errno. In the error case, dwc
  128. * may contain some buffers allocated but not all which were requested.
  129. */
  130. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  131. {
  132. int num;
  133. int i;
  134. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  135. dwc->num_event_buffers = num;
  136. dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
  137. sizeof(*dwc->ev_buffs) * num);
  138. if (!dwc->ev_buffs)
  139. return -ENOMEM;
  140. for (i = 0; i < num; i++) {
  141. struct dwc3_event_buffer *evt;
  142. evt = dwc3_alloc_one_event_buffer(dwc, length);
  143. if (IS_ERR(evt)) {
  144. dev_err(dwc->dev, "can't allocate event buffer\n");
  145. return PTR_ERR(evt);
  146. }
  147. dwc->ev_buffs[i] = evt;
  148. }
  149. return 0;
  150. }
  151. /**
  152. * dwc3_event_buffers_setup - setup our allocated event buffers
  153. * @dwc: pointer to our controller context structure
  154. *
  155. * Returns 0 on success otherwise negative errno.
  156. */
  157. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  158. {
  159. struct dwc3_event_buffer *evt;
  160. int n;
  161. for (n = 0; n < dwc->num_event_buffers; n++) {
  162. evt = dwc->ev_buffs[n];
  163. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  164. evt->buf, (unsigned long long) evt->dma,
  165. evt->length);
  166. evt->lpos = 0;
  167. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  168. lower_32_bits(evt->dma));
  169. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  170. upper_32_bits(evt->dma));
  171. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  172. DWC3_GEVNTSIZ_SIZE(evt->length));
  173. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  174. }
  175. return 0;
  176. }
  177. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  178. {
  179. struct dwc3_event_buffer *evt;
  180. int n;
  181. for (n = 0; n < dwc->num_event_buffers; n++) {
  182. evt = dwc->ev_buffs[n];
  183. evt->lpos = 0;
  184. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  185. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  186. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
  187. | DWC3_GEVNTSIZ_SIZE(0));
  188. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  189. }
  190. }
  191. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  192. {
  193. if (!dwc->has_hibernation)
  194. return 0;
  195. if (!dwc->nr_scratch)
  196. return 0;
  197. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  198. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  199. if (!dwc->scratchbuf)
  200. return -ENOMEM;
  201. return 0;
  202. }
  203. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  204. {
  205. dma_addr_t scratch_addr;
  206. u32 param;
  207. int ret;
  208. if (!dwc->has_hibernation)
  209. return 0;
  210. if (!dwc->nr_scratch)
  211. return 0;
  212. scratch_addr = dma_map_single(dwc->scratchbuf,
  213. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  214. DMA_BIDIRECTIONAL);
  215. if (dma_mapping_error(dwc->dev, scratch_addr)) {
  216. dev_err(dwc->dev, "failed to map scratch buffer\n");
  217. ret = -EFAULT;
  218. goto err0;
  219. }
  220. dwc->scratch_addr = scratch_addr;
  221. param = lower_32_bits(scratch_addr);
  222. ret = dwc3_send_gadget_generic_command(dwc,
  223. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  224. if (ret < 0)
  225. goto err1;
  226. param = upper_32_bits(scratch_addr);
  227. ret = dwc3_send_gadget_generic_command(dwc,
  228. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  229. if (ret < 0)
  230. goto err1;
  231. return 0;
  232. err1:
  233. dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
  234. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  235. err0:
  236. return ret;
  237. }
  238. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  239. {
  240. if (!dwc->has_hibernation)
  241. return;
  242. if (!dwc->nr_scratch)
  243. return;
  244. dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
  245. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  246. kfree(dwc->scratchbuf);
  247. }
  248. static void dwc3_core_num_eps(struct dwc3 *dwc)
  249. {
  250. struct dwc3_hwparams *parms = &dwc->hwparams;
  251. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  252. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  253. dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
  254. dwc->num_in_eps, dwc->num_out_eps);
  255. }
  256. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  257. {
  258. struct dwc3_hwparams *parms = &dwc->hwparams;
  259. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  260. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  261. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  262. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  263. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  264. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  265. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  266. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  267. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  268. }
  269. /**
  270. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  271. * @dwc: Pointer to our controller context structure
  272. */
  273. static void dwc3_phy_setup(struct dwc3 *dwc)
  274. {
  275. u32 reg;
  276. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  277. /*
  278. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  279. * to '0' during coreConsultant configuration. So default value
  280. * will be '0' when the core is reset. Application needs to set it
  281. * to '1' after the core initialization is completed.
  282. */
  283. if (dwc->revision > DWC3_REVISION_194A)
  284. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  285. if (dwc->u2ss_inp3_quirk)
  286. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  287. if (dwc->req_p1p2p3_quirk)
  288. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  289. if (dwc->del_p1p2p3_quirk)
  290. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  291. if (dwc->del_phy_power_chg_quirk)
  292. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  293. if (dwc->lfps_filter_quirk)
  294. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  295. if (dwc->rx_detect_poll_quirk)
  296. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  297. if (dwc->tx_de_emphasis_quirk)
  298. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  299. if (dwc->dis_u3_susphy_quirk)
  300. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  301. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  302. mdelay(100);
  303. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  304. /*
  305. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  306. * '0' during coreConsultant configuration. So default value will
  307. * be '0' when the core is reset. Application needs to set it to
  308. * '1' after the core initialization is completed.
  309. */
  310. if (dwc->revision > DWC3_REVISION_194A)
  311. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  312. if (dwc->dis_u2_susphy_quirk)
  313. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  314. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  315. mdelay(100);
  316. }
  317. /**
  318. * dwc3_core_init - Low-level initialization of DWC3 Core
  319. * @dwc: Pointer to our controller context structure
  320. *
  321. * Returns 0 on success otherwise negative errno.
  322. */
  323. static int dwc3_core_init(struct dwc3 *dwc)
  324. {
  325. unsigned long timeout;
  326. u32 hwparams4 = dwc->hwparams.hwparams4;
  327. u32 reg;
  328. int ret;
  329. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  330. /* This should read as U3 followed by revision number */
  331. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  332. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  333. ret = -ENODEV;
  334. goto err0;
  335. }
  336. dwc->revision = reg;
  337. /* Handle USB2.0-only core configuration */
  338. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  339. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  340. if (dwc->maximum_speed == USB_SPEED_SUPER)
  341. dwc->maximum_speed = USB_SPEED_HIGH;
  342. }
  343. /* issue device SoftReset too */
  344. timeout = 5000;
  345. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  346. while (timeout--) {
  347. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  348. if (!(reg & DWC3_DCTL_CSFTRST))
  349. break;
  350. };
  351. if (!timeout) {
  352. dev_err(dwc->dev, "Reset Timed Out\n");
  353. ret = -ETIMEDOUT;
  354. goto err0;
  355. }
  356. dwc3_phy_setup(dwc);
  357. ret = dwc3_core_soft_reset(dwc);
  358. if (ret)
  359. goto err0;
  360. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  361. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  362. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  363. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  364. /**
  365. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  366. * issue which would cause xHCI compliance tests to fail.
  367. *
  368. * Because of that we cannot enable clock gating on such
  369. * configurations.
  370. *
  371. * Refers to:
  372. *
  373. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  374. * SOF/ITP Mode Used
  375. */
  376. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  377. dwc->dr_mode == USB_DR_MODE_OTG) &&
  378. (dwc->revision >= DWC3_REVISION_210A &&
  379. dwc->revision <= DWC3_REVISION_250A))
  380. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  381. else
  382. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  383. break;
  384. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  385. /* enable hibernation here */
  386. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  387. /*
  388. * REVISIT Enabling this bit so that host-mode hibernation
  389. * will work. Device-mode hibernation is not yet implemented.
  390. */
  391. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  392. break;
  393. default:
  394. dev_dbg(dwc->dev, "No power optimization available\n");
  395. }
  396. /* check if current dwc3 is on simulation board */
  397. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  398. dev_dbg(dwc->dev, "it is on FPGA board\n");
  399. dwc->is_fpga = true;
  400. }
  401. if(dwc->disable_scramble_quirk && !dwc->is_fpga)
  402. WARN(true,
  403. "disable_scramble cannot be used on non-FPGA builds\n");
  404. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  405. reg |= DWC3_GCTL_DISSCRAMBLE;
  406. else
  407. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  408. if (dwc->u2exit_lfps_quirk)
  409. reg |= DWC3_GCTL_U2EXIT_LFPS;
  410. /*
  411. * WORKAROUND: DWC3 revisions <1.90a have a bug
  412. * where the device can fail to connect at SuperSpeed
  413. * and falls back to high-speed mode which causes
  414. * the device to enter a Connect/Disconnect loop
  415. */
  416. if (dwc->revision < DWC3_REVISION_190A)
  417. reg |= DWC3_GCTL_U2RSTECN;
  418. dwc3_core_num_eps(dwc);
  419. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  420. ret = dwc3_alloc_scratch_buffers(dwc);
  421. if (ret)
  422. goto err0;
  423. ret = dwc3_setup_scratch_buffers(dwc);
  424. if (ret)
  425. goto err1;
  426. return 0;
  427. err1:
  428. dwc3_free_scratch_buffers(dwc);
  429. err0:
  430. return ret;
  431. }
  432. static void dwc3_core_exit(struct dwc3 *dwc)
  433. {
  434. dwc3_free_scratch_buffers(dwc);
  435. }
  436. static int dwc3_core_init_mode(struct dwc3 *dwc)
  437. {
  438. int ret;
  439. switch (dwc->dr_mode) {
  440. case USB_DR_MODE_PERIPHERAL:
  441. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  442. ret = dwc3_gadget_init(dwc);
  443. if (ret) {
  444. dev_err(dev, "failed to initialize gadget\n");
  445. return ret;
  446. }
  447. break;
  448. case USB_DR_MODE_HOST:
  449. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  450. ret = dwc3_host_init(dwc);
  451. if (ret) {
  452. dev_err(dev, "failed to initialize host\n");
  453. return ret;
  454. }
  455. break;
  456. case USB_DR_MODE_OTG:
  457. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  458. ret = dwc3_host_init(dwc);
  459. if (ret) {
  460. dev_err(dev, "failed to initialize host\n");
  461. return ret;
  462. }
  463. ret = dwc3_gadget_init(dwc);
  464. if (ret) {
  465. dev_err(dev, "failed to initialize gadget\n");
  466. return ret;
  467. }
  468. break;
  469. default:
  470. dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  471. return -EINVAL;
  472. }
  473. return 0;
  474. }
  475. static void dwc3_gadget_run(struct dwc3 *dwc)
  476. {
  477. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
  478. mdelay(100);
  479. }
  480. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  481. {
  482. switch (dwc->dr_mode) {
  483. case USB_DR_MODE_PERIPHERAL:
  484. dwc3_gadget_exit(dwc);
  485. break;
  486. case USB_DR_MODE_HOST:
  487. dwc3_host_exit(dwc);
  488. break;
  489. case USB_DR_MODE_OTG:
  490. dwc3_host_exit(dwc);
  491. dwc3_gadget_exit(dwc);
  492. break;
  493. default:
  494. /* do nothing */
  495. break;
  496. }
  497. /*
  498. * switch back to peripheral mode
  499. * This enables the phy to enter idle and then, if enabled, suspend.
  500. */
  501. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  502. dwc3_gadget_run(dwc);
  503. }
  504. static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
  505. struct dwc3 *dwc)
  506. {
  507. enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
  508. u32 reg;
  509. /* Set dwc3 usb2 phy config */
  510. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  511. reg |= DWC3_GUSB2PHYCFG_PHYIF;
  512. reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  513. switch (hsphy_mode) {
  514. case USBPHY_INTERFACE_MODE_UTMI:
  515. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
  516. break;
  517. case USBPHY_INTERFACE_MODE_UTMIW:
  518. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
  519. break;
  520. default:
  521. break;
  522. }
  523. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  524. }
  525. #define DWC3_ALIGN_MASK (16 - 1)
  526. /**
  527. * dwc3_uboot_init - dwc3 core uboot initialization code
  528. * @dwc3_dev: struct dwc3_device containing initialization data
  529. *
  530. * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
  531. * kernel driver). Pointer to dwc3_device should be passed containing
  532. * base address and other initialization data. Returns '0' on success and
  533. * a negative value on failure.
  534. *
  535. * Generally called from board_usb_init() implemented in board file.
  536. */
  537. int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
  538. {
  539. struct dwc3 *dwc;
  540. struct device *dev = NULL;
  541. u8 lpm_nyet_threshold;
  542. u8 tx_de_emphasis;
  543. u8 hird_threshold;
  544. int ret;
  545. void *mem;
  546. mem = devm_kzalloc((struct udevice *)dev,
  547. sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  548. if (!mem)
  549. return -ENOMEM;
  550. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  551. dwc->mem = mem;
  552. dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
  553. DWC3_GLOBALS_REGS_START);
  554. /* default to highest possible threshold */
  555. lpm_nyet_threshold = 0xff;
  556. /* default to -3.5dB de-emphasis */
  557. tx_de_emphasis = 1;
  558. /*
  559. * default to assert utmi_sleep_n and use maximum allowed HIRD
  560. * threshold value of 0b1100
  561. */
  562. hird_threshold = 12;
  563. dwc->maximum_speed = dwc3_dev->maximum_speed;
  564. dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
  565. if (dwc3_dev->lpm_nyet_threshold)
  566. lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
  567. dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
  568. if (dwc3_dev->hird_threshold)
  569. hird_threshold = dwc3_dev->hird_threshold;
  570. dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
  571. dwc->dr_mode = dwc3_dev->dr_mode;
  572. dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
  573. dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
  574. dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
  575. dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
  576. dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
  577. dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
  578. dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
  579. dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
  580. dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
  581. dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
  582. dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
  583. if (dwc3_dev->tx_de_emphasis)
  584. tx_de_emphasis = dwc3_dev->tx_de_emphasis;
  585. /* default to superspeed if no maximum_speed passed */
  586. if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
  587. dwc->maximum_speed = USB_SPEED_SUPER;
  588. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  589. dwc->tx_de_emphasis = tx_de_emphasis;
  590. dwc->hird_threshold = hird_threshold
  591. | (dwc->is_utmi_l1_suspend << 4);
  592. dwc->index = dwc3_dev->index;
  593. dwc3_cache_hwparams(dwc);
  594. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  595. if (ret) {
  596. dev_err(dwc->dev, "failed to allocate event buffers\n");
  597. return -ENOMEM;
  598. }
  599. if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  600. dwc->dr_mode = USB_DR_MODE_HOST;
  601. else if (!IS_ENABLED(CONFIG_USB_HOST))
  602. dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
  603. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  604. dwc->dr_mode = USB_DR_MODE_OTG;
  605. ret = dwc3_core_init(dwc);
  606. if (ret) {
  607. dev_err(dev, "failed to initialize core\n");
  608. goto err0;
  609. }
  610. dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
  611. ret = dwc3_event_buffers_setup(dwc);
  612. if (ret) {
  613. dev_err(dwc->dev, "failed to setup event buffers\n");
  614. goto err1;
  615. }
  616. ret = dwc3_core_init_mode(dwc);
  617. if (ret)
  618. goto err2;
  619. list_add_tail(&dwc->list, &dwc3_list);
  620. return 0;
  621. err2:
  622. dwc3_event_buffers_cleanup(dwc);
  623. err1:
  624. dwc3_core_exit(dwc);
  625. err0:
  626. dwc3_free_event_buffers(dwc);
  627. return ret;
  628. }
  629. /**
  630. * dwc3_uboot_exit - dwc3 core uboot cleanup code
  631. * @index: index of this controller
  632. *
  633. * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
  634. * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
  635. * should be passed and should match with the index passed in
  636. * dwc3_device during init.
  637. *
  638. * Generally called from board file.
  639. */
  640. void dwc3_uboot_exit(int index)
  641. {
  642. struct dwc3 *dwc;
  643. list_for_each_entry(dwc, &dwc3_list, list) {
  644. if (dwc->index != index)
  645. continue;
  646. dwc3_core_exit_mode(dwc);
  647. dwc3_event_buffers_cleanup(dwc);
  648. dwc3_free_event_buffers(dwc);
  649. dwc3_core_exit(dwc);
  650. list_del(&dwc->list);
  651. kfree(dwc->mem);
  652. break;
  653. }
  654. }
  655. /**
  656. * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
  657. * @index: index of this controller
  658. *
  659. * Invokes dwc3 gadget interrupts.
  660. *
  661. * Generally called from board file.
  662. */
  663. void dwc3_uboot_handle_interrupt(int index)
  664. {
  665. struct dwc3 *dwc = NULL;
  666. list_for_each_entry(dwc, &dwc3_list, list) {
  667. if (dwc->index != index)
  668. continue;
  669. dwc3_gadget_uboot_handle_interrupt(dwc);
  670. break;
  671. }
  672. }
  673. MODULE_ALIAS("platform:dwc3");
  674. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  675. MODULE_LICENSE("GPL v2");
  676. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  677. #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
  678. int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
  679. {
  680. int i, ret, count;
  681. struct phy *usb_phys;
  682. /* Return if no phy declared */
  683. if (!dev_read_prop(dev, "phys", NULL))
  684. return 0;
  685. count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
  686. if (count <= 0)
  687. return count;
  688. usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
  689. GFP_KERNEL);
  690. if (!usb_phys)
  691. return -ENOMEM;
  692. for (i = 0; i < count; i++) {
  693. ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
  694. if (ret && ret != -ENOENT) {
  695. pr_err("Failed to get USB PHY%d for %s\n",
  696. i, dev->name);
  697. return ret;
  698. }
  699. }
  700. for (i = 0; i < count; i++) {
  701. ret = generic_phy_init(&usb_phys[i]);
  702. if (ret) {
  703. pr_err("Can't init USB PHY%d for %s\n",
  704. i, dev->name);
  705. goto phys_init_err;
  706. }
  707. }
  708. for (i = 0; i < count; i++) {
  709. ret = generic_phy_power_on(&usb_phys[i]);
  710. if (ret) {
  711. pr_err("Can't power USB PHY%d for %s\n",
  712. i, dev->name);
  713. goto phys_poweron_err;
  714. }
  715. }
  716. *array = usb_phys;
  717. *num_phys = count;
  718. return 0;
  719. phys_poweron_err:
  720. for (i = count - 1; i >= 0; i--)
  721. generic_phy_power_off(&usb_phys[i]);
  722. for (i = 0; i < count; i++)
  723. generic_phy_exit(&usb_phys[i]);
  724. return ret;
  725. phys_init_err:
  726. for (; i >= 0; i--)
  727. generic_phy_exit(&usb_phys[i]);
  728. return ret;
  729. }
  730. int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
  731. {
  732. int i, ret;
  733. for (i = 0; i < num_phys; i++) {
  734. if (!generic_phy_valid(&usb_phys[i]))
  735. continue;
  736. ret = generic_phy_power_off(&usb_phys[i]);
  737. ret |= generic_phy_exit(&usb_phys[i]);
  738. if (ret) {
  739. pr_err("Can't shutdown USB PHY%d for %s\n",
  740. i, dev->name);
  741. }
  742. }
  743. return 0;
  744. }
  745. #endif
  746. #if CONFIG_IS_ENABLED(DM_USB)
  747. void dwc3_of_parse(struct dwc3 *dwc)
  748. {
  749. const u8 *tmp;
  750. struct udevice *dev = dwc->dev;
  751. u8 lpm_nyet_threshold;
  752. u8 tx_de_emphasis;
  753. u8 hird_threshold;
  754. /* default to highest possible threshold */
  755. lpm_nyet_threshold = 0xff;
  756. /* default to -3.5dB de-emphasis */
  757. tx_de_emphasis = 1;
  758. /*
  759. * default to assert utmi_sleep_n and use maximum allowed HIRD
  760. * threshold value of 0b1100
  761. */
  762. hird_threshold = 12;
  763. dwc->has_lpm_erratum = dev_read_bool(dev,
  764. "snps,has-lpm-erratum");
  765. tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
  766. if (tmp)
  767. lpm_nyet_threshold = *tmp;
  768. dwc->is_utmi_l1_suspend = dev_read_bool(dev,
  769. "snps,is-utmi-l1-suspend");
  770. tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
  771. if (tmp)
  772. hird_threshold = *tmp;
  773. dwc->disable_scramble_quirk = dev_read_bool(dev,
  774. "snps,disable_scramble_quirk");
  775. dwc->u2exit_lfps_quirk = dev_read_bool(dev,
  776. "snps,u2exit_lfps_quirk");
  777. dwc->u2ss_inp3_quirk = dev_read_bool(dev,
  778. "snps,u2ss_inp3_quirk");
  779. dwc->req_p1p2p3_quirk = dev_read_bool(dev,
  780. "snps,req_p1p2p3_quirk");
  781. dwc->del_p1p2p3_quirk = dev_read_bool(dev,
  782. "snps,del_p1p2p3_quirk");
  783. dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
  784. "snps,del_phy_power_chg_quirk");
  785. dwc->lfps_filter_quirk = dev_read_bool(dev,
  786. "snps,lfps_filter_quirk");
  787. dwc->rx_detect_poll_quirk = dev_read_bool(dev,
  788. "snps,rx_detect_poll_quirk");
  789. dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
  790. "snps,dis_u3_susphy_quirk");
  791. dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
  792. "snps,dis_u2_susphy_quirk");
  793. dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
  794. "snps,tx_de_emphasis_quirk");
  795. tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
  796. if (tmp)
  797. tx_de_emphasis = *tmp;
  798. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  799. dwc->tx_de_emphasis = tx_de_emphasis;
  800. dwc->hird_threshold = hird_threshold
  801. | (dwc->is_utmi_l1_suspend << 4);
  802. }
  803. int dwc3_init(struct dwc3 *dwc)
  804. {
  805. int ret;
  806. dwc3_cache_hwparams(dwc);
  807. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  808. if (ret) {
  809. dev_err(dwc->dev, "failed to allocate event buffers\n");
  810. return -ENOMEM;
  811. }
  812. ret = dwc3_core_init(dwc);
  813. if (ret) {
  814. dev_err(dev, "failed to initialize core\n");
  815. goto core_fail;
  816. }
  817. ret = dwc3_event_buffers_setup(dwc);
  818. if (ret) {
  819. dev_err(dwc->dev, "failed to setup event buffers\n");
  820. goto event_fail;
  821. }
  822. ret = dwc3_core_init_mode(dwc);
  823. if (ret)
  824. goto mode_fail;
  825. return 0;
  826. mode_fail:
  827. dwc3_event_buffers_cleanup(dwc);
  828. event_fail:
  829. dwc3_core_exit(dwc);
  830. core_fail:
  831. dwc3_free_event_buffers(dwc);
  832. return ret;
  833. }
  834. void dwc3_remove(struct dwc3 *dwc)
  835. {
  836. dwc3_core_exit_mode(dwc);
  837. dwc3_event_buffers_cleanup(dwc);
  838. dwc3_free_event_buffers(dwc);
  839. dwc3_core_exit(dwc);
  840. kfree(dwc->mem);
  841. }
  842. #endif