rawnand.h 39 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271
  1. /*
  2. * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
  3. * Steven J. Hill <sjhill@realitydiluted.com>
  4. * Thomas Gleixner <tglx@linutronix.de>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. *
  8. * Info:
  9. * Contains standard defines and IDs for NAND flash devices
  10. *
  11. * Changelog:
  12. * See git changelog.
  13. */
  14. #ifndef __LINUX_MTD_RAWNAND_H
  15. #define __LINUX_MTD_RAWNAND_H
  16. #include <config.h>
  17. #include <linux/compat.h>
  18. #include <linux/mtd/mtd.h>
  19. #include <linux/mtd/flashchip.h>
  20. #include <linux/mtd/bbm.h>
  21. struct mtd_info;
  22. struct nand_flash_dev;
  23. struct device_node;
  24. /* Scan and identify a NAND device */
  25. int nand_scan(struct mtd_info *mtd, int max_chips);
  26. /*
  27. * Separate phases of nand_scan(), allowing board driver to intervene
  28. * and override command or ECC setup according to flash type.
  29. */
  30. int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  31. struct nand_flash_dev *table);
  32. int nand_scan_tail(struct mtd_info *mtd);
  33. /* Free resources held by the NAND device */
  34. void nand_release(struct mtd_info *mtd);
  35. /* Internal helper for board drivers which need to override command function */
  36. void nand_wait_ready(struct mtd_info *mtd);
  37. /*
  38. * This constant declares the max. oobsize / page, which
  39. * is supported now. If you add a chip with bigger oobsize/page
  40. * adjust this accordingly.
  41. */
  42. #define NAND_MAX_OOBSIZE 1664
  43. #define NAND_MAX_PAGESIZE 16384
  44. /*
  45. * Constants for hardware specific CLE/ALE/NCE function
  46. *
  47. * These are bits which can be or'ed to set/clear multiple
  48. * bits in one go.
  49. */
  50. /* Select the chip by setting nCE to low */
  51. #define NAND_NCE 0x01
  52. /* Select the command latch by setting CLE to high */
  53. #define NAND_CLE 0x02
  54. /* Select the address latch by setting ALE to high */
  55. #define NAND_ALE 0x04
  56. #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
  57. #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
  58. #define NAND_CTRL_CHANGE 0x80
  59. /*
  60. * Standard NAND flash commands
  61. */
  62. #define NAND_CMD_READ0 0
  63. #define NAND_CMD_READ1 1
  64. #define NAND_CMD_RNDOUT 5
  65. #define NAND_CMD_PAGEPROG 0x10
  66. #define NAND_CMD_READOOB 0x50
  67. #define NAND_CMD_ERASE1 0x60
  68. #define NAND_CMD_STATUS 0x70
  69. #define NAND_CMD_SEQIN 0x80
  70. #define NAND_CMD_RNDIN 0x85
  71. #define NAND_CMD_READID 0x90
  72. #define NAND_CMD_ERASE2 0xd0
  73. #define NAND_CMD_PARAM 0xec
  74. #define NAND_CMD_GET_FEATURES 0xee
  75. #define NAND_CMD_SET_FEATURES 0xef
  76. #define NAND_CMD_RESET 0xff
  77. #define NAND_CMD_LOCK 0x2a
  78. #define NAND_CMD_UNLOCK1 0x23
  79. #define NAND_CMD_UNLOCK2 0x24
  80. /* Extended commands for large page devices */
  81. #define NAND_CMD_READSTART 0x30
  82. #define NAND_CMD_RNDOUTSTART 0xE0
  83. #define NAND_CMD_CACHEDPROG 0x15
  84. /* Extended commands for AG-AND device */
  85. /*
  86. * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  87. * there is no way to distinguish that from NAND_CMD_READ0
  88. * until the remaining sequence of commands has been completed
  89. * so add a high order bit and mask it off in the command.
  90. */
  91. #define NAND_CMD_DEPLETE1 0x100
  92. #define NAND_CMD_DEPLETE2 0x38
  93. #define NAND_CMD_STATUS_MULTI 0x71
  94. #define NAND_CMD_STATUS_ERROR 0x72
  95. /* multi-bank error status (banks 0-3) */
  96. #define NAND_CMD_STATUS_ERROR0 0x73
  97. #define NAND_CMD_STATUS_ERROR1 0x74
  98. #define NAND_CMD_STATUS_ERROR2 0x75
  99. #define NAND_CMD_STATUS_ERROR3 0x76
  100. #define NAND_CMD_STATUS_RESET 0x7f
  101. #define NAND_CMD_STATUS_CLEAR 0xff
  102. #define NAND_CMD_NONE -1
  103. /* Status bits */
  104. #define NAND_STATUS_FAIL 0x01
  105. #define NAND_STATUS_FAIL_N1 0x02
  106. #define NAND_STATUS_TRUE_READY 0x20
  107. #define NAND_STATUS_READY 0x40
  108. #define NAND_STATUS_WP 0x80
  109. #define NAND_DATA_IFACE_CHECK_ONLY -1
  110. /*
  111. * Constants for ECC_MODES
  112. */
  113. typedef enum {
  114. NAND_ECC_NONE,
  115. NAND_ECC_SOFT,
  116. NAND_ECC_HW,
  117. NAND_ECC_HW_SYNDROME,
  118. NAND_ECC_HW_OOB_FIRST,
  119. NAND_ECC_SOFT_BCH,
  120. } nand_ecc_modes_t;
  121. /*
  122. * Constants for Hardware ECC
  123. */
  124. /* Reset Hardware ECC for read */
  125. #define NAND_ECC_READ 0
  126. /* Reset Hardware ECC for write */
  127. #define NAND_ECC_WRITE 1
  128. /* Enable Hardware ECC before syndrome is read back from flash */
  129. #define NAND_ECC_READSYN 2
  130. /*
  131. * Enable generic NAND 'page erased' check. This check is only done when
  132. * ecc.correct() returns -EBADMSG.
  133. * Set this flag if your implementation does not fix bitflips in erased
  134. * pages and you want to rely on the default implementation.
  135. */
  136. #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
  137. #define NAND_ECC_MAXIMIZE BIT(1)
  138. /*
  139. * If your controller already sends the required NAND commands when
  140. * reading or writing a page, then the framework is not supposed to
  141. * send READ0 and SEQIN/PAGEPROG respectively.
  142. */
  143. #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
  144. /* Bit mask for flags passed to do_nand_read_ecc */
  145. #define NAND_GET_DEVICE 0x80
  146. /*
  147. * Option constants for bizarre disfunctionality and real
  148. * features.
  149. */
  150. /* Buswidth is 16 bit */
  151. #define NAND_BUSWIDTH_16 0x00000002
  152. /* Device supports partial programming without padding */
  153. #define NAND_NO_PADDING 0x00000004
  154. /* Chip has cache program function */
  155. #define NAND_CACHEPRG 0x00000008
  156. /* Chip has copy back function */
  157. #define NAND_COPYBACK 0x00000010
  158. /*
  159. * Chip requires ready check on read (for auto-incremented sequential read).
  160. * True only for small page devices; large page devices do not support
  161. * autoincrement.
  162. */
  163. #define NAND_NEED_READRDY 0x00000100
  164. /* Chip does not allow subpage writes */
  165. #define NAND_NO_SUBPAGE_WRITE 0x00000200
  166. /* Device is one of 'new' xD cards that expose fake nand command set */
  167. #define NAND_BROKEN_XD 0x00000400
  168. /* Device behaves just like nand, but is readonly */
  169. #define NAND_ROM 0x00000800
  170. /* Device supports subpage reads */
  171. #define NAND_SUBPAGE_READ 0x00001000
  172. /*
  173. * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
  174. * patterns.
  175. */
  176. #define NAND_NEED_SCRAMBLING 0x00002000
  177. /* Device needs 3rd row address cycle */
  178. #define NAND_ROW_ADDR_3 0x00004000
  179. /* Options valid for Samsung large page devices */
  180. #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
  181. /* Macros to identify the above */
  182. #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  183. #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
  184. #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
  185. /* Non chip related options */
  186. /* This option skips the bbt scan during initialization. */
  187. #define NAND_SKIP_BBTSCAN 0x00010000
  188. /*
  189. * This option is defined if the board driver allocates its own buffers
  190. * (e.g. because it needs them DMA-coherent).
  191. */
  192. #define NAND_OWN_BUFFERS 0x00020000
  193. /* Chip may not exist, so silence any errors in scan */
  194. #define NAND_SCAN_SILENT_NODEV 0x00040000
  195. /*
  196. * Autodetect nand buswidth with readid/onfi.
  197. * This suppose the driver will configure the hardware in 8 bits mode
  198. * when calling nand_scan_ident, and update its configuration
  199. * before calling nand_scan_tail.
  200. */
  201. #define NAND_BUSWIDTH_AUTO 0x00080000
  202. /*
  203. * This option could be defined by controller drivers to protect against
  204. * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
  205. */
  206. #define NAND_USE_BOUNCE_BUFFER 0x00100000
  207. /* Options set by nand scan */
  208. /* bbt has already been read */
  209. #define NAND_BBT_SCANNED 0x40000000
  210. /* Nand scan has allocated controller struct */
  211. #define NAND_CONTROLLER_ALLOC 0x80000000
  212. /* Cell info constants */
  213. #define NAND_CI_CHIPNR_MSK 0x03
  214. #define NAND_CI_CELLTYPE_MSK 0x0C
  215. #define NAND_CI_CELLTYPE_SHIFT 2
  216. /* Keep gcc happy */
  217. struct nand_chip;
  218. /* ONFI features */
  219. #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
  220. #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
  221. /* ONFI timing mode, used in both asynchronous and synchronous mode */
  222. #define ONFI_TIMING_MODE_0 (1 << 0)
  223. #define ONFI_TIMING_MODE_1 (1 << 1)
  224. #define ONFI_TIMING_MODE_2 (1 << 2)
  225. #define ONFI_TIMING_MODE_3 (1 << 3)
  226. #define ONFI_TIMING_MODE_4 (1 << 4)
  227. #define ONFI_TIMING_MODE_5 (1 << 5)
  228. #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
  229. /* ONFI feature address */
  230. #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
  231. /* Vendor-specific feature address (Micron) */
  232. #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
  233. /* ONFI subfeature parameters length */
  234. #define ONFI_SUBFEATURE_PARAM_LEN 4
  235. /* ONFI optional commands SET/GET FEATURES supported? */
  236. #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
  237. struct nand_onfi_params {
  238. /* rev info and features block */
  239. /* 'O' 'N' 'F' 'I' */
  240. u8 sig[4];
  241. __le16 revision;
  242. __le16 features;
  243. __le16 opt_cmd;
  244. u8 reserved0[2];
  245. __le16 ext_param_page_length; /* since ONFI 2.1 */
  246. u8 num_of_param_pages; /* since ONFI 2.1 */
  247. u8 reserved1[17];
  248. /* manufacturer information block */
  249. char manufacturer[12];
  250. char model[20];
  251. u8 jedec_id;
  252. __le16 date_code;
  253. u8 reserved2[13];
  254. /* memory organization block */
  255. __le32 byte_per_page;
  256. __le16 spare_bytes_per_page;
  257. __le32 data_bytes_per_ppage;
  258. __le16 spare_bytes_per_ppage;
  259. __le32 pages_per_block;
  260. __le32 blocks_per_lun;
  261. u8 lun_count;
  262. u8 addr_cycles;
  263. u8 bits_per_cell;
  264. __le16 bb_per_lun;
  265. __le16 block_endurance;
  266. u8 guaranteed_good_blocks;
  267. __le16 guaranteed_block_endurance;
  268. u8 programs_per_page;
  269. u8 ppage_attr;
  270. u8 ecc_bits;
  271. u8 interleaved_bits;
  272. u8 interleaved_ops;
  273. u8 reserved3[13];
  274. /* electrical parameter block */
  275. u8 io_pin_capacitance_max;
  276. __le16 async_timing_mode;
  277. __le16 program_cache_timing_mode;
  278. __le16 t_prog;
  279. __le16 t_bers;
  280. __le16 t_r;
  281. __le16 t_ccs;
  282. __le16 src_sync_timing_mode;
  283. u8 src_ssync_features;
  284. __le16 clk_pin_capacitance_typ;
  285. __le16 io_pin_capacitance_typ;
  286. __le16 input_pin_capacitance_typ;
  287. u8 input_pin_capacitance_max;
  288. u8 driver_strength_support;
  289. __le16 t_int_r;
  290. __le16 t_adl;
  291. u8 reserved4[8];
  292. /* vendor */
  293. __le16 vendor_revision;
  294. u8 vendor[88];
  295. __le16 crc;
  296. } __packed;
  297. #define ONFI_CRC_BASE 0x4F4E
  298. /* Extended ECC information Block Definition (since ONFI 2.1) */
  299. struct onfi_ext_ecc_info {
  300. u8 ecc_bits;
  301. u8 codeword_size;
  302. __le16 bb_per_lun;
  303. __le16 block_endurance;
  304. u8 reserved[2];
  305. } __packed;
  306. #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
  307. #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
  308. #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
  309. struct onfi_ext_section {
  310. u8 type;
  311. u8 length;
  312. } __packed;
  313. #define ONFI_EXT_SECTION_MAX 8
  314. /* Extended Parameter Page Definition (since ONFI 2.1) */
  315. struct onfi_ext_param_page {
  316. __le16 crc;
  317. u8 sig[4]; /* 'E' 'P' 'P' 'S' */
  318. u8 reserved0[10];
  319. struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
  320. /*
  321. * The actual size of the Extended Parameter Page is in
  322. * @ext_param_page_length of nand_onfi_params{}.
  323. * The following are the variable length sections.
  324. * So we do not add any fields below. Please see the ONFI spec.
  325. */
  326. } __packed;
  327. struct nand_onfi_vendor_micron {
  328. u8 two_plane_read;
  329. u8 read_cache;
  330. u8 read_unique_id;
  331. u8 dq_imped;
  332. u8 dq_imped_num_settings;
  333. u8 dq_imped_feat_addr;
  334. u8 rb_pulldown_strength;
  335. u8 rb_pulldown_strength_feat_addr;
  336. u8 rb_pulldown_strength_num_settings;
  337. u8 otp_mode;
  338. u8 otp_page_start;
  339. u8 otp_data_prot_addr;
  340. u8 otp_num_pages;
  341. u8 otp_feat_addr;
  342. u8 read_retry_options;
  343. u8 reserved[72];
  344. u8 param_revision;
  345. } __packed;
  346. struct jedec_ecc_info {
  347. u8 ecc_bits;
  348. u8 codeword_size;
  349. __le16 bb_per_lun;
  350. __le16 block_endurance;
  351. u8 reserved[2];
  352. } __packed;
  353. /* JEDEC features */
  354. #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
  355. struct nand_jedec_params {
  356. /* rev info and features block */
  357. /* 'J' 'E' 'S' 'D' */
  358. u8 sig[4];
  359. __le16 revision;
  360. __le16 features;
  361. u8 opt_cmd[3];
  362. __le16 sec_cmd;
  363. u8 num_of_param_pages;
  364. u8 reserved0[18];
  365. /* manufacturer information block */
  366. char manufacturer[12];
  367. char model[20];
  368. u8 jedec_id[6];
  369. u8 reserved1[10];
  370. /* memory organization block */
  371. __le32 byte_per_page;
  372. __le16 spare_bytes_per_page;
  373. u8 reserved2[6];
  374. __le32 pages_per_block;
  375. __le32 blocks_per_lun;
  376. u8 lun_count;
  377. u8 addr_cycles;
  378. u8 bits_per_cell;
  379. u8 programs_per_page;
  380. u8 multi_plane_addr;
  381. u8 multi_plane_op_attr;
  382. u8 reserved3[38];
  383. /* electrical parameter block */
  384. __le16 async_sdr_speed_grade;
  385. __le16 toggle_ddr_speed_grade;
  386. __le16 sync_ddr_speed_grade;
  387. u8 async_sdr_features;
  388. u8 toggle_ddr_features;
  389. u8 sync_ddr_features;
  390. __le16 t_prog;
  391. __le16 t_bers;
  392. __le16 t_r;
  393. __le16 t_r_multi_plane;
  394. __le16 t_ccs;
  395. __le16 io_pin_capacitance_typ;
  396. __le16 input_pin_capacitance_typ;
  397. __le16 clk_pin_capacitance_typ;
  398. u8 driver_strength_support;
  399. __le16 t_adl;
  400. u8 reserved4[36];
  401. /* ECC and endurance block */
  402. u8 guaranteed_good_blocks;
  403. __le16 guaranteed_block_endurance;
  404. struct jedec_ecc_info ecc_info[4];
  405. u8 reserved5[29];
  406. /* reserved */
  407. u8 reserved6[148];
  408. /* vendor */
  409. __le16 vendor_rev_num;
  410. u8 reserved7[88];
  411. /* CRC for Parameter Page */
  412. __le16 crc;
  413. } __packed;
  414. /**
  415. * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  416. * @lock: protection lock
  417. * @active: the mtd device which holds the controller currently
  418. * @wq: wait queue to sleep on if a NAND operation is in
  419. * progress used instead of the per chip wait queue
  420. * when a hw controller is available.
  421. */
  422. struct nand_hw_control {
  423. spinlock_t lock;
  424. struct nand_chip *active;
  425. };
  426. /**
  427. * struct nand_ecc_step_info - ECC step information of ECC engine
  428. * @stepsize: data bytes per ECC step
  429. * @strengths: array of supported strengths
  430. * @nstrengths: number of supported strengths
  431. */
  432. struct nand_ecc_step_info {
  433. int stepsize;
  434. const int *strengths;
  435. int nstrengths;
  436. };
  437. /**
  438. * struct nand_ecc_caps - capability of ECC engine
  439. * @stepinfos: array of ECC step information
  440. * @nstepinfos: number of ECC step information
  441. * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
  442. */
  443. struct nand_ecc_caps {
  444. const struct nand_ecc_step_info *stepinfos;
  445. int nstepinfos;
  446. int (*calc_ecc_bytes)(int step_size, int strength);
  447. };
  448. /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
  449. #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
  450. static const int __name##_strengths[] = { __VA_ARGS__ }; \
  451. static const struct nand_ecc_step_info __name##_stepinfo = { \
  452. .stepsize = __step, \
  453. .strengths = __name##_strengths, \
  454. .nstrengths = ARRAY_SIZE(__name##_strengths), \
  455. }; \
  456. static const struct nand_ecc_caps __name = { \
  457. .stepinfos = &__name##_stepinfo, \
  458. .nstepinfos = 1, \
  459. .calc_ecc_bytes = __calc, \
  460. }
  461. /**
  462. * struct nand_ecc_ctrl - Control structure for ECC
  463. * @mode: ECC mode
  464. * @steps: number of ECC steps per page
  465. * @size: data bytes per ECC step
  466. * @bytes: ECC bytes per step
  467. * @strength: max number of correctible bits per ECC step
  468. * @total: total number of ECC bytes per page
  469. * @prepad: padding information for syndrome based ECC generators
  470. * @postpad: padding information for syndrome based ECC generators
  471. * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
  472. * @layout: ECC layout control struct pointer
  473. * @priv: pointer to private ECC control data
  474. * @hwctl: function to control hardware ECC generator. Must only
  475. * be provided if an hardware ECC is available
  476. * @calculate: function for ECC calculation or readback from ECC hardware
  477. * @correct: function for ECC correction, matching to ECC generator (sw/hw).
  478. * Should return a positive number representing the number of
  479. * corrected bitflips, -EBADMSG if the number of bitflips exceed
  480. * ECC strength, or any other error code if the error is not
  481. * directly related to correction.
  482. * If -EBADMSG is returned the input buffers should be left
  483. * untouched.
  484. * @read_page_raw: function to read a raw page without ECC. This function
  485. * should hide the specific layout used by the ECC
  486. * controller and always return contiguous in-band and
  487. * out-of-band data even if they're not stored
  488. * contiguously on the NAND chip (e.g.
  489. * NAND_ECC_HW_SYNDROME interleaves in-band and
  490. * out-of-band data).
  491. * @write_page_raw: function to write a raw page without ECC. This function
  492. * should hide the specific layout used by the ECC
  493. * controller and consider the passed data as contiguous
  494. * in-band and out-of-band data. ECC controller is
  495. * responsible for doing the appropriate transformations
  496. * to adapt to its specific layout (e.g.
  497. * NAND_ECC_HW_SYNDROME interleaves in-band and
  498. * out-of-band data).
  499. * @read_page: function to read a page according to the ECC generator
  500. * requirements; returns maximum number of bitflips corrected in
  501. * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
  502. * @read_subpage: function to read parts of the page covered by ECC;
  503. * returns same as read_page()
  504. * @write_subpage: function to write parts of the page covered by ECC.
  505. * @write_page: function to write a page according to the ECC generator
  506. * requirements.
  507. * @write_oob_raw: function to write chip OOB data without ECC
  508. * @read_oob_raw: function to read chip OOB data without ECC
  509. * @read_oob: function to read chip OOB data
  510. * @write_oob: function to write chip OOB data
  511. */
  512. struct nand_ecc_ctrl {
  513. nand_ecc_modes_t mode;
  514. int steps;
  515. int size;
  516. int bytes;
  517. int total;
  518. int strength;
  519. int prepad;
  520. int postpad;
  521. unsigned int options;
  522. struct nand_ecclayout *layout;
  523. void *priv;
  524. void (*hwctl)(struct mtd_info *mtd, int mode);
  525. int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
  526. uint8_t *ecc_code);
  527. int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
  528. uint8_t *calc_ecc);
  529. int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  530. uint8_t *buf, int oob_required, int page);
  531. int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  532. const uint8_t *buf, int oob_required, int page);
  533. int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
  534. uint8_t *buf, int oob_required, int page);
  535. int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  536. uint32_t offs, uint32_t len, uint8_t *buf, int page);
  537. int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  538. uint32_t offset, uint32_t data_len,
  539. const uint8_t *data_buf, int oob_required, int page);
  540. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  541. const uint8_t *buf, int oob_required, int page);
  542. int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  543. int page);
  544. int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  545. int page);
  546. int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
  547. int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
  548. int page);
  549. };
  550. static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
  551. {
  552. return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
  553. }
  554. /**
  555. * struct nand_buffers - buffer structure for read/write
  556. * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
  557. * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
  558. * @databuf: buffer pointer for data, size is (page size + oobsize).
  559. *
  560. * Do not change the order of buffers. databuf and oobrbuf must be in
  561. * consecutive order.
  562. */
  563. struct nand_buffers {
  564. uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  565. uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  566. uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
  567. ARCH_DMA_MINALIGN)];
  568. };
  569. /**
  570. * struct nand_sdr_timings - SDR NAND chip timings
  571. *
  572. * This struct defines the timing requirements of a SDR NAND chip.
  573. * These information can be found in every NAND datasheets and the timings
  574. * meaning are described in the ONFI specifications:
  575. * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
  576. * Parameters)
  577. *
  578. * All these timings are expressed in picoseconds.
  579. *
  580. * @tBERS_max: Block erase time
  581. * @tCCS_min: Change column setup time
  582. * @tPROG_max: Page program time
  583. * @tR_max: Page read time
  584. * @tALH_min: ALE hold time
  585. * @tADL_min: ALE to data loading time
  586. * @tALS_min: ALE setup time
  587. * @tAR_min: ALE to RE# delay
  588. * @tCEA_max: CE# access time
  589. * @tCEH_min: CE# high hold time
  590. * @tCH_min: CE# hold time
  591. * @tCHZ_max: CE# high to output hi-Z
  592. * @tCLH_min: CLE hold time
  593. * @tCLR_min: CLE to RE# delay
  594. * @tCLS_min: CLE setup time
  595. * @tCOH_min: CE# high to output hold
  596. * @tCS_min: CE# setup time
  597. * @tDH_min: Data hold time
  598. * @tDS_min: Data setup time
  599. * @tFEAT_max: Busy time for Set Features and Get Features
  600. * @tIR_min: Output hi-Z to RE# low
  601. * @tITC_max: Interface and Timing Mode Change time
  602. * @tRC_min: RE# cycle time
  603. * @tREA_max: RE# access time
  604. * @tREH_min: RE# high hold time
  605. * @tRHOH_min: RE# high to output hold
  606. * @tRHW_min: RE# high to WE# low
  607. * @tRHZ_max: RE# high to output hi-Z
  608. * @tRLOH_min: RE# low to output hold
  609. * @tRP_min: RE# pulse width
  610. * @tRR_min: Ready to RE# low (data only)
  611. * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
  612. * rising edge of R/B#.
  613. * @tWB_max: WE# high to SR[6] low
  614. * @tWC_min: WE# cycle time
  615. * @tWH_min: WE# high hold time
  616. * @tWHR_min: WE# high to RE# low
  617. * @tWP_min: WE# pulse width
  618. * @tWW_min: WP# transition to WE# low
  619. */
  620. struct nand_sdr_timings {
  621. u64 tBERS_max;
  622. u32 tCCS_min;
  623. u64 tPROG_max;
  624. u64 tR_max;
  625. u32 tALH_min;
  626. u32 tADL_min;
  627. u32 tALS_min;
  628. u32 tAR_min;
  629. u32 tCEA_max;
  630. u32 tCEH_min;
  631. u32 tCH_min;
  632. u32 tCHZ_max;
  633. u32 tCLH_min;
  634. u32 tCLR_min;
  635. u32 tCLS_min;
  636. u32 tCOH_min;
  637. u32 tCS_min;
  638. u32 tDH_min;
  639. u32 tDS_min;
  640. u32 tFEAT_max;
  641. u32 tIR_min;
  642. u32 tITC_max;
  643. u32 tRC_min;
  644. u32 tREA_max;
  645. u32 tREH_min;
  646. u32 tRHOH_min;
  647. u32 tRHW_min;
  648. u32 tRHZ_max;
  649. u32 tRLOH_min;
  650. u32 tRP_min;
  651. u32 tRR_min;
  652. u64 tRST_max;
  653. u32 tWB_max;
  654. u32 tWC_min;
  655. u32 tWH_min;
  656. u32 tWHR_min;
  657. u32 tWP_min;
  658. u32 tWW_min;
  659. };
  660. /**
  661. * enum nand_data_interface_type - NAND interface timing type
  662. * @NAND_SDR_IFACE: Single Data Rate interface
  663. */
  664. enum nand_data_interface_type {
  665. NAND_SDR_IFACE,
  666. };
  667. /**
  668. * struct nand_data_interface - NAND interface timing
  669. * @type: type of the timing
  670. * @timings: The timing, type according to @type
  671. */
  672. struct nand_data_interface {
  673. enum nand_data_interface_type type;
  674. union {
  675. struct nand_sdr_timings sdr;
  676. } timings;
  677. };
  678. /**
  679. * nand_get_sdr_timings - get SDR timing from data interface
  680. * @conf: The data interface
  681. */
  682. static inline const struct nand_sdr_timings *
  683. nand_get_sdr_timings(const struct nand_data_interface *conf)
  684. {
  685. if (conf->type != NAND_SDR_IFACE)
  686. return ERR_PTR(-EINVAL);
  687. return &conf->timings.sdr;
  688. }
  689. /**
  690. * struct nand_chip - NAND Private Flash Chip Data
  691. * @mtd: MTD device registered to the MTD framework
  692. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
  693. * flash device
  694. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
  695. * flash device.
  696. * @flash_node: [BOARDSPECIFIC] device node describing this instance
  697. * @read_byte: [REPLACEABLE] read one byte from the chip
  698. * @read_word: [REPLACEABLE] read one word from the chip
  699. * @write_byte: [REPLACEABLE] write a single byte to the chip on the
  700. * low 8 I/O lines
  701. * @write_buf: [REPLACEABLE] write data from the buffer to the chip
  702. * @read_buf: [REPLACEABLE] read data from the chip into the buffer
  703. * @select_chip: [REPLACEABLE] select chip nr
  704. * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
  705. * @block_markbad: [REPLACEABLE] mark a block bad
  706. * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
  707. * ALE/CLE/nCE. Also used to write command and address
  708. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
  709. * device ready/busy line. If set to NULL no access to
  710. * ready/busy is available and the ready/busy information
  711. * is read from the chip status register.
  712. * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
  713. * commands to the chip.
  714. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
  715. * ready.
  716. * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
  717. * setting the read-retry mode. Mostly needed for MLC NAND.
  718. * @ecc: [BOARDSPECIFIC] ECC control structure
  719. * @buffers: buffer structure for read/write
  720. * @buf_align: minimum buffer alignment required by a platform
  721. * @hwcontrol: platform-specific hardware control structure
  722. * @erase: [REPLACEABLE] erase function
  723. * @scan_bbt: [REPLACEABLE] function to scan bad block table
  724. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
  725. * data from array to read regs (tR).
  726. * @state: [INTERN] the current state of the NAND device
  727. * @oob_poi: "poison value buffer," used for laying out OOB data
  728. * before writing
  729. * @page_shift: [INTERN] number of address bits in a page (column
  730. * address bits).
  731. * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
  732. * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
  733. * @chip_shift: [INTERN] number of address bits in one chip
  734. * @options: [BOARDSPECIFIC] various chip options. They can partly
  735. * be set to inform nand_scan about special functionality.
  736. * See the defines for further explanation.
  737. * @bbt_options: [INTERN] bad block specific options. All options used
  738. * here must come from bbm.h. By default, these options
  739. * will be copied to the appropriate nand_bbt_descr's.
  740. * @badblockpos: [INTERN] position of the bad block marker in the oob
  741. * area.
  742. * @badblockbits: [INTERN] minimum number of set bits in a good block's
  743. * bad block marker position; i.e., BBM == 11110111b is
  744. * not bad when badblockbits == 7
  745. * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
  746. * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
  747. * Minimum amount of bit errors per @ecc_step_ds guaranteed
  748. * to be correctable. If unknown, set to zero.
  749. * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
  750. * also from the datasheet. It is the recommended ECC step
  751. * size, if known; if unknown, set to zero.
  752. * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
  753. * set to the actually used ONFI mode if the chip is
  754. * ONFI compliant or deduced from the datasheet if
  755. * the NAND chip is not ONFI compliant.
  756. * @numchips: [INTERN] number of physical chips
  757. * @chipsize: [INTERN] the size of one chip for multichip arrays
  758. * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
  759. * @pagebuf: [INTERN] holds the pagenumber which is currently in
  760. * data_buf.
  761. * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
  762. * currently in data_buf.
  763. * @subpagesize: [INTERN] holds the subpagesize
  764. * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
  765. * non 0 if ONFI supported.
  766. * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
  767. * non 0 if JEDEC supported.
  768. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
  769. * supported, 0 otherwise.
  770. * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
  771. * supported, 0 otherwise.
  772. * @read_retries: [INTERN] the number of read retry modes supported
  773. * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
  774. * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
  775. * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
  776. * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
  777. * means the configuration should not be applied but
  778. * only checked.
  779. * @bbt: [INTERN] bad block table pointer
  780. * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
  781. * lookup.
  782. * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
  783. * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
  784. * bad block scan.
  785. * @controller: [REPLACEABLE] a pointer to a hardware controller
  786. * structure which is shared among multiple independent
  787. * devices.
  788. * @priv: [OPTIONAL] pointer to private chip data
  789. * @write_page: [REPLACEABLE] High-level page write function
  790. */
  791. struct nand_chip {
  792. struct mtd_info mtd;
  793. void __iomem *IO_ADDR_R;
  794. void __iomem *IO_ADDR_W;
  795. int flash_node;
  796. uint8_t (*read_byte)(struct mtd_info *mtd);
  797. u16 (*read_word)(struct mtd_info *mtd);
  798. void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
  799. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  800. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  801. void (*select_chip)(struct mtd_info *mtd, int chip);
  802. int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
  803. int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  804. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  805. int (*dev_ready)(struct mtd_info *mtd);
  806. void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
  807. int page_addr);
  808. int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  809. int (*erase)(struct mtd_info *mtd, int page);
  810. int (*scan_bbt)(struct mtd_info *mtd);
  811. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  812. uint32_t offset, int data_len, const uint8_t *buf,
  813. int oob_required, int page, int raw);
  814. int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
  815. int feature_addr, uint8_t *subfeature_para);
  816. int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
  817. int feature_addr, uint8_t *subfeature_para);
  818. int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
  819. int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
  820. const struct nand_data_interface *conf);
  821. int chip_delay;
  822. unsigned int options;
  823. unsigned int bbt_options;
  824. int page_shift;
  825. int phys_erase_shift;
  826. int bbt_erase_shift;
  827. int chip_shift;
  828. int numchips;
  829. uint64_t chipsize;
  830. int pagemask;
  831. int pagebuf;
  832. unsigned int pagebuf_bitflips;
  833. int subpagesize;
  834. uint8_t bits_per_cell;
  835. uint16_t ecc_strength_ds;
  836. uint16_t ecc_step_ds;
  837. int onfi_timing_mode_default;
  838. int badblockpos;
  839. int badblockbits;
  840. int onfi_version;
  841. int jedec_version;
  842. struct nand_onfi_params onfi_params;
  843. struct nand_jedec_params jedec_params;
  844. struct nand_data_interface *data_interface;
  845. int read_retries;
  846. flstate_t state;
  847. uint8_t *oob_poi;
  848. struct nand_hw_control *controller;
  849. struct nand_ecclayout *ecclayout;
  850. struct nand_ecc_ctrl ecc;
  851. struct nand_buffers *buffers;
  852. unsigned long buf_align;
  853. struct nand_hw_control hwcontrol;
  854. uint8_t *bbt;
  855. struct nand_bbt_descr *bbt_td;
  856. struct nand_bbt_descr *bbt_md;
  857. struct nand_bbt_descr *badblock_pattern;
  858. void *priv;
  859. };
  860. static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
  861. {
  862. return container_of(mtd, struct nand_chip, mtd);
  863. }
  864. static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
  865. {
  866. return &chip->mtd;
  867. }
  868. static inline void *nand_get_controller_data(struct nand_chip *chip)
  869. {
  870. return chip->priv;
  871. }
  872. static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
  873. {
  874. chip->priv = priv;
  875. }
  876. /*
  877. * NAND Flash Manufacturer ID Codes
  878. */
  879. #define NAND_MFR_TOSHIBA 0x98
  880. #define NAND_MFR_SAMSUNG 0xec
  881. #define NAND_MFR_FUJITSU 0x04
  882. #define NAND_MFR_NATIONAL 0x8f
  883. #define NAND_MFR_RENESAS 0x07
  884. #define NAND_MFR_STMICRO 0x20
  885. #define NAND_MFR_HYNIX 0xad
  886. #define NAND_MFR_MICRON 0x2c
  887. #define NAND_MFR_AMD 0x01
  888. #define NAND_MFR_MACRONIX 0xc2
  889. #define NAND_MFR_EON 0x92
  890. #define NAND_MFR_SANDISK 0x45
  891. #define NAND_MFR_INTEL 0x89
  892. #define NAND_MFR_ATO 0x9b
  893. /* The maximum expected count of bytes in the NAND ID sequence */
  894. #define NAND_MAX_ID_LEN 8
  895. /*
  896. * A helper for defining older NAND chips where the second ID byte fully
  897. * defined the chip, including the geometry (chip size, eraseblock size, page
  898. * size). All these chips have 512 bytes NAND page size.
  899. */
  900. #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
  901. { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
  902. .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
  903. /*
  904. * A helper for defining newer chips which report their page size and
  905. * eraseblock size via the extended ID bytes.
  906. *
  907. * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
  908. * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
  909. * device ID now only represented a particular total chip size (and voltage,
  910. * buswidth), and the page size, eraseblock size, and OOB size could vary while
  911. * using the same device ID.
  912. */
  913. #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
  914. { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
  915. .options = (opts) }
  916. #define NAND_ECC_INFO(_strength, _step) \
  917. { .strength_ds = (_strength), .step_ds = (_step) }
  918. #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
  919. #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
  920. /**
  921. * struct nand_flash_dev - NAND Flash Device ID Structure
  922. * @name: a human-readable name of the NAND chip
  923. * @dev_id: the device ID (the second byte of the full chip ID array)
  924. * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
  925. * memory address as @id[0])
  926. * @dev_id: device ID part of the full chip ID array (refers the same memory
  927. * address as @id[1])
  928. * @id: full device ID array
  929. * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
  930. * well as the eraseblock size) is determined from the extended NAND
  931. * chip ID array)
  932. * @chipsize: total chip size in MiB
  933. * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
  934. * @options: stores various chip bit options
  935. * @id_len: The valid length of the @id.
  936. * @oobsize: OOB size
  937. * @ecc: ECC correctability and step information from the datasheet.
  938. * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  939. * @ecc_strength_ds in nand_chip{}.
  940. * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  941. * @ecc_step_ds in nand_chip{}, also from the datasheet.
  942. * For example, the "4bit ECC for each 512Byte" can be set with
  943. * NAND_ECC_INFO(4, 512).
  944. * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
  945. * reset. Should be deduced from timings described
  946. * in the datasheet.
  947. *
  948. */
  949. struct nand_flash_dev {
  950. char *name;
  951. union {
  952. struct {
  953. uint8_t mfr_id;
  954. uint8_t dev_id;
  955. };
  956. uint8_t id[NAND_MAX_ID_LEN];
  957. };
  958. unsigned int pagesize;
  959. unsigned int chipsize;
  960. unsigned int erasesize;
  961. unsigned int options;
  962. uint16_t id_len;
  963. uint16_t oobsize;
  964. struct {
  965. uint16_t strength_ds;
  966. uint16_t step_ds;
  967. } ecc;
  968. int onfi_timing_mode_default;
  969. };
  970. /**
  971. * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  972. * @name: Manufacturer name
  973. * @id: manufacturer ID code of device.
  974. */
  975. struct nand_manufacturers {
  976. int id;
  977. char *name;
  978. };
  979. extern struct nand_flash_dev nand_flash_ids[];
  980. extern struct nand_manufacturers nand_manuf_ids[];
  981. int nand_default_bbt(struct mtd_info *mtd);
  982. int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
  983. int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
  984. int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  985. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  986. int allowbbt);
  987. int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  988. size_t *retlen, uint8_t *buf);
  989. /*
  990. * Constants for oob configuration
  991. */
  992. #define NAND_SMALL_BADBLOCK_POS 5
  993. #define NAND_LARGE_BADBLOCK_POS 0
  994. /**
  995. * struct platform_nand_chip - chip level device structure
  996. * @nr_chips: max. number of chips to scan for
  997. * @chip_offset: chip number offset
  998. * @nr_partitions: number of partitions pointed to by partitions (or zero)
  999. * @partitions: mtd partition list
  1000. * @chip_delay: R/B delay value in us
  1001. * @options: Option flags, e.g. 16bit buswidth
  1002. * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
  1003. * @part_probe_types: NULL-terminated array of probe types
  1004. */
  1005. struct platform_nand_chip {
  1006. int nr_chips;
  1007. int chip_offset;
  1008. int nr_partitions;
  1009. struct mtd_partition *partitions;
  1010. int chip_delay;
  1011. unsigned int options;
  1012. unsigned int bbt_options;
  1013. const char **part_probe_types;
  1014. };
  1015. /* Keep gcc happy */
  1016. struct platform_device;
  1017. /**
  1018. * struct platform_nand_ctrl - controller level device structure
  1019. * @probe: platform specific function to probe/setup hardware
  1020. * @remove: platform specific function to remove/teardown hardware
  1021. * @hwcontrol: platform specific hardware control structure
  1022. * @dev_ready: platform specific function to read ready/busy pin
  1023. * @select_chip: platform specific chip select function
  1024. * @cmd_ctrl: platform specific function for controlling
  1025. * ALE/CLE/nCE. Also used to write command and address
  1026. * @write_buf: platform specific function for write buffer
  1027. * @read_buf: platform specific function for read buffer
  1028. * @read_byte: platform specific function to read one byte from chip
  1029. * @priv: private data to transport driver specific settings
  1030. *
  1031. * All fields are optional and depend on the hardware driver requirements
  1032. */
  1033. struct platform_nand_ctrl {
  1034. int (*probe)(struct platform_device *pdev);
  1035. void (*remove)(struct platform_device *pdev);
  1036. void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  1037. int (*dev_ready)(struct mtd_info *mtd);
  1038. void (*select_chip)(struct mtd_info *mtd, int chip);
  1039. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  1040. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  1041. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  1042. unsigned char (*read_byte)(struct mtd_info *mtd);
  1043. void *priv;
  1044. };
  1045. /**
  1046. * struct platform_nand_data - container structure for platform-specific data
  1047. * @chip: chip level chip structure
  1048. * @ctrl: controller level device structure
  1049. */
  1050. struct platform_nand_data {
  1051. struct platform_nand_chip chip;
  1052. struct platform_nand_ctrl ctrl;
  1053. };
  1054. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  1055. /* return the supported features. */
  1056. static inline int onfi_feature(struct nand_chip *chip)
  1057. {
  1058. return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
  1059. }
  1060. /* return the supported asynchronous timing mode. */
  1061. static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  1062. {
  1063. if (!chip->onfi_version)
  1064. return ONFI_TIMING_MODE_UNKNOWN;
  1065. return le16_to_cpu(chip->onfi_params.async_timing_mode);
  1066. }
  1067. /* return the supported synchronous timing mode. */
  1068. static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  1069. {
  1070. if (!chip->onfi_version)
  1071. return ONFI_TIMING_MODE_UNKNOWN;
  1072. return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
  1073. }
  1074. #else
  1075. static inline int onfi_feature(struct nand_chip *chip)
  1076. {
  1077. return 0;
  1078. }
  1079. static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  1080. {
  1081. return ONFI_TIMING_MODE_UNKNOWN;
  1082. }
  1083. static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  1084. {
  1085. return ONFI_TIMING_MODE_UNKNOWN;
  1086. }
  1087. #endif
  1088. int onfi_init_data_interface(struct nand_chip *chip,
  1089. struct nand_data_interface *iface,
  1090. enum nand_data_interface_type type,
  1091. int timing_mode);
  1092. /*
  1093. * Check if it is a SLC nand.
  1094. * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
  1095. * We do not distinguish the MLC and TLC now.
  1096. */
  1097. static inline bool nand_is_slc(struct nand_chip *chip)
  1098. {
  1099. return chip->bits_per_cell == 1;
  1100. }
  1101. /**
  1102. * Check if the opcode's address should be sent only on the lower 8 bits
  1103. * @command: opcode to check
  1104. */
  1105. static inline int nand_opcode_8bits(unsigned int command)
  1106. {
  1107. switch (command) {
  1108. case NAND_CMD_READID:
  1109. case NAND_CMD_PARAM:
  1110. case NAND_CMD_GET_FEATURES:
  1111. case NAND_CMD_SET_FEATURES:
  1112. return 1;
  1113. default:
  1114. break;
  1115. }
  1116. return 0;
  1117. }
  1118. /* return the supported JEDEC features. */
  1119. static inline int jedec_feature(struct nand_chip *chip)
  1120. {
  1121. return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
  1122. : 0;
  1123. }
  1124. /* Standard NAND functions from nand_base.c */
  1125. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
  1126. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
  1127. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
  1128. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
  1129. uint8_t nand_read_byte(struct mtd_info *mtd);
  1130. /* get timing characteristics from ONFI timing mode. */
  1131. const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
  1132. /* get data interface from ONFI timing mode 0, used after reset. */
  1133. const struct nand_data_interface *nand_get_default_data_interface(void);
  1134. int nand_check_erased_ecc_chunk(void *data, int datalen,
  1135. void *ecc, int ecclen,
  1136. void *extraoob, int extraooblen,
  1137. int threshold);
  1138. int nand_check_ecc_caps(struct nand_chip *chip,
  1139. const struct nand_ecc_caps *caps, int oobavail);
  1140. int nand_match_ecc_req(struct nand_chip *chip,
  1141. const struct nand_ecc_caps *caps, int oobavail);
  1142. int nand_maximize_ecc(struct nand_chip *chip,
  1143. const struct nand_ecc_caps *caps, int oobavail);
  1144. /* Reset and initialize a NAND device */
  1145. int nand_reset(struct nand_chip *chip, int chipnr);
  1146. #endif /* __LINUX_MTD_RAWNAND_H */