fsmc_nand.h 2.1 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485
  1. /*
  2. * (C) Copyright 2010
  3. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef __FSMC_NAND_H__
  8. #define __FSMC_NAND_H__
  9. #include <linux/mtd/rawnand.h>
  10. struct fsmc_regs {
  11. u32 ctrl; /* 0x00 */
  12. u8 reserved_1[0x40 - 0x04];
  13. u32 pc; /* 0x40 */
  14. u32 sts; /* 0x44 */
  15. u32 comm; /* 0x48 */
  16. u32 attrib; /* 0x4c */
  17. u32 ioata; /* 0x50 */
  18. u32 ecc1; /* 0x54 */
  19. u32 ecc2; /* 0x58 */
  20. u32 ecc3; /* 0x5c */
  21. u8 reserved_2[0xfe0 - 0x60];
  22. u32 peripid0; /* 0xfe0 */
  23. u32 peripid1; /* 0xfe4 */
  24. u32 peripid2; /* 0xfe8 */
  25. u32 peripid3; /* 0xfec */
  26. u32 pcellid0; /* 0xff0 */
  27. u32 pcellid1; /* 0xff4 */
  28. u32 pcellid2; /* 0xff8 */
  29. u32 pcellid3; /* 0xffc */
  30. };
  31. /* ctrl register definitions */
  32. #define FSMC_WP (1 << 7)
  33. /* pc register definitions */
  34. #define FSMC_RESET (1 << 0)
  35. #define FSMC_WAITON (1 << 1)
  36. #define FSMC_ENABLE (1 << 2)
  37. #define FSMC_DEVTYPE_NAND (1 << 3)
  38. #define FSMC_DEVWID_8 (0 << 4)
  39. #define FSMC_DEVWID_16 (1 << 4)
  40. #define FSMC_ECCEN (1 << 6)
  41. #define FSMC_ECCPLEN_512 (0 << 7)
  42. #define FSMC_ECCPLEN_256 (1 << 7)
  43. #define FSMC_TCLR_1 (1 << 9)
  44. #define FSMC_TAR_1 (1 << 13)
  45. /* sts register definitions */
  46. #define FSMC_CODE_RDY (1 << 15)
  47. /* comm register definitions */
  48. #define FSMC_TSET_0 (0 << 0)
  49. #define FSMC_TWAIT_6 (6 << 8)
  50. #define FSMC_THOLD_4 (4 << 16)
  51. #define FSMC_THIZ_1 (1 << 24)
  52. /* peripid2 register definitions */
  53. #define FSMC_REVISION_MSK (0xf)
  54. #define FSMC_REVISION_SHFT (0x4)
  55. #define FSMC_VER8 0x8
  56. /*
  57. * There are 13 bytes of ecc for every 512 byte block and it has to be read
  58. * consecutively and immediately after the 512 byte data block for hardware to
  59. * generate the error bit offsets
  60. * Managing the ecc bytes in the following way is easier. This way is similar to
  61. * oobfree structure maintained already in u-boot nand driver
  62. */
  63. #define FSMC_MAX_ECCPLACE_ENTRIES 32
  64. struct fsmc_nand_eccplace {
  65. u32 offset;
  66. u32 length;
  67. };
  68. struct fsmc_eccplace {
  69. struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
  70. };
  71. extern int fsmc_nand_init(struct nand_chip *nand);
  72. #endif