zynq_nand.c 33 KB

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  1. /*
  2. * (C) Copyright 2016 Xilinx, Inc.
  3. *
  4. * Xilinx Zynq NAND Flash Controller Driver
  5. * This driver is based on plat_nand.c and mxc_nand.c drivers
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <asm/io.h>
  12. #include <linux/errno.h>
  13. #include <nand.h>
  14. #include <linux/mtd/mtd.h>
  15. #include <linux/mtd/rawnand.h>
  16. #include <linux/mtd/partitions.h>
  17. #include <linux/mtd/nand_ecc.h>
  18. #include <asm/arch/hardware.h>
  19. /* The NAND flash driver defines */
  20. #define ZYNQ_NAND_CMD_PHASE 1
  21. #define ZYNQ_NAND_DATA_PHASE 2
  22. #define ZYNQ_NAND_ECC_SIZE 512
  23. #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
  24. #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
  25. #define ZYNQ_NAND_ECC_STATUS (1 << 6)
  26. #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
  27. #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
  28. #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
  29. #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
  30. /* Flash memory controller operating parameters */
  31. #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
  32. (0x1 << 4) | /* Clear interrupt */ \
  33. (0x1 << 6)) /* Disable ECC interrupt */
  34. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  35. /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  36. #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
  37. (0x2 << 17) | /* t_ar from nand_cycles */ \
  38. (0x1 << 14) | /* t_clr from nand_cycles */ \
  39. (0x3 << 11) | /* t_wp from nand_cycles */ \
  40. (0x2 << 8) | /* t_rea from nand_cycles */ \
  41. (0x5 << 4) | /* t_wc from nand_cycles */ \
  42. (0x5 << 0)) /* t_rc from nand_cycles */
  43. #endif
  44. #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
  45. (0x2 << 21)) /* UpdateRegs operation */
  46. #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
  47. (0x1 << 4) | /* ECC read at end of page */ \
  48. (0x0 << 5)) /* No Jumping */
  49. #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
  50. (0x00 << 8) | /* Read command */ \
  51. (0x30 << 16) | /* Read End command */ \
  52. (0x1 << 24)) /* Read End command calid */
  53. #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
  54. (0x05 << 8) | /* Read col change cmd */ \
  55. (0xE0 << 16) | /* Read col change end cmd */ \
  56. (0x1 << 24)) /* Read col change
  57. end cmd valid */
  58. /* AXI Address definitions */
  59. #define START_CMD_SHIFT 3
  60. #define END_CMD_SHIFT 11
  61. #define END_CMD_VALID_SHIFT 20
  62. #define ADDR_CYCLES_SHIFT 21
  63. #define CLEAR_CS_SHIFT 21
  64. #define ECC_LAST_SHIFT 10
  65. #define COMMAND_PHASE (0 << 19)
  66. #define DATA_PHASE (1 << 19)
  67. #define ONDIE_ECC_FEATURE_ADDR 0x90
  68. #define ONDIE_ECC_FEATURE_ENABLE 0x08
  69. #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
  70. #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
  71. /* ECC block registers bit position and bit mask */
  72. #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
  73. #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
  74. #ifndef NAND_CMD_LOCK_TIGHT
  75. #define NAND_CMD_LOCK_TIGHT 0x2c
  76. #endif
  77. #ifndef NAND_CMD_LOCK_STATUS
  78. #define NAND_CMD_LOCK_STATUS 0x7a
  79. #endif
  80. /* SMC register set */
  81. struct zynq_nand_smc_regs {
  82. u32 csr; /* 0x00 */
  83. u32 reserved0[2];
  84. u32 cfr; /* 0x0C */
  85. u32 dcr; /* 0x10 */
  86. u32 scr; /* 0x14 */
  87. u32 sor; /* 0x18 */
  88. u32 reserved1[249];
  89. u32 esr; /* 0x400 */
  90. u32 emcr; /* 0x404 */
  91. u32 emcmd1r; /* 0x408 */
  92. u32 emcmd2r; /* 0x40C */
  93. u32 reserved2[2];
  94. u32 eval0r; /* 0x418 */
  95. };
  96. #define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\
  97. ZYNQ_SMC_BASEADDR)
  98. /*
  99. * struct zynq_nand_info - Defines the NAND flash driver instance
  100. * @parts: Pointer to the mtd_partition structure
  101. * @nand_base: Virtual address of the NAND flash device
  102. * @end_cmd_pending: End command is pending
  103. * @end_cmd: End command
  104. */
  105. struct zynq_nand_info {
  106. void __iomem *nand_base;
  107. u8 end_cmd_pending;
  108. u8 end_cmd;
  109. };
  110. /*
  111. * struct zynq_nand_command_format - Defines NAND flash command format
  112. * @start_cmd: First cycle command (Start command)
  113. * @end_cmd: Second cycle command (Last command)
  114. * @addr_cycles: Number of address cycles required to send the address
  115. * @end_cmd_valid: The second cycle command is valid for cmd or data phase
  116. */
  117. struct zynq_nand_command_format {
  118. u8 start_cmd;
  119. u8 end_cmd;
  120. u8 addr_cycles;
  121. u8 end_cmd_valid;
  122. };
  123. /* The NAND flash operations command format */
  124. static const struct zynq_nand_command_format zynq_nand_commands[] = {
  125. {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
  126. {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
  127. {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
  128. {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
  129. {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
  130. {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
  131. {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
  132. {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
  133. {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
  134. {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
  135. {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
  136. {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
  137. {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
  138. {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
  139. {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
  140. {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
  141. {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
  142. /* Add all the flash commands supported by the flash device */
  143. };
  144. /* Define default oob placement schemes for large and small page devices */
  145. static struct nand_ecclayout nand_oob_16 = {
  146. .eccbytes = 3,
  147. .eccpos = {0, 1, 2},
  148. .oobfree = {
  149. { .offset = 8, .length = 8 }
  150. }
  151. };
  152. static struct nand_ecclayout nand_oob_64 = {
  153. .eccbytes = 12,
  154. .eccpos = {
  155. 52, 53, 54, 55, 56, 57,
  156. 58, 59, 60, 61, 62, 63},
  157. .oobfree = {
  158. { .offset = 2, .length = 50 }
  159. }
  160. };
  161. static struct nand_ecclayout ondie_nand_oob_64 = {
  162. .eccbytes = 32,
  163. .eccpos = {
  164. 8, 9, 10, 11, 12, 13, 14, 15,
  165. 24, 25, 26, 27, 28, 29, 30, 31,
  166. 40, 41, 42, 43, 44, 45, 46, 47,
  167. 56, 57, 58, 59, 60, 61, 62, 63
  168. },
  169. .oobfree = {
  170. { .offset = 4, .length = 4 },
  171. { .offset = 20, .length = 4 },
  172. { .offset = 36, .length = 4 },
  173. { .offset = 52, .length = 4 }
  174. }
  175. };
  176. /* bbt decriptors for chips with on-die ECC and
  177. chips with 64-byte OOB */
  178. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  179. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  180. static struct nand_bbt_descr bbt_main_descr = {
  181. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  182. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  183. .offs = 4,
  184. .len = 4,
  185. .veroffs = 20,
  186. .maxblocks = 4,
  187. .pattern = bbt_pattern
  188. };
  189. static struct nand_bbt_descr bbt_mirror_descr = {
  190. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  191. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  192. .offs = 4,
  193. .len = 4,
  194. .veroffs = 20,
  195. .maxblocks = 4,
  196. .pattern = mirror_pattern
  197. };
  198. /*
  199. * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
  200. *
  201. * returns: status for command completion, -1 for Timeout
  202. */
  203. static int zynq_nand_waitfor_ecc_completion(void)
  204. {
  205. unsigned long timeout;
  206. u32 status;
  207. /* Wait max 10us */
  208. timeout = 10;
  209. status = readl(&zynq_nand_smc_base->esr);
  210. while (status & ZYNQ_NAND_ECC_BUSY) {
  211. status = readl(&zynq_nand_smc_base->esr);
  212. if (timeout == 0)
  213. return -1;
  214. timeout--;
  215. udelay(1);
  216. }
  217. return status;
  218. }
  219. /*
  220. * zynq_nand_init_nand_flash - Initialize NAND controller
  221. * @option: Device property flags
  222. *
  223. * This function initializes the NAND flash interface on the NAND controller.
  224. *
  225. * returns: 0 on success or error value on failure
  226. */
  227. static int zynq_nand_init_nand_flash(int option)
  228. {
  229. u32 status;
  230. /* disable interrupts */
  231. writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
  232. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  233. /* Initialize the NAND interface by setting cycles and operation mode */
  234. writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
  235. #endif
  236. if (option & NAND_BUSWIDTH_16)
  237. writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
  238. else
  239. writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
  240. writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
  241. /* Wait till the ECC operation is complete */
  242. status = zynq_nand_waitfor_ecc_completion();
  243. if (status < 0) {
  244. printf("%s: Timeout\n", __func__);
  245. return status;
  246. }
  247. /* Set the command1 and command2 register */
  248. writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
  249. writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
  250. return 0;
  251. }
  252. /*
  253. * zynq_nand_calculate_hwecc - Calculate Hardware ECC
  254. * @mtd: Pointer to the mtd_info structure
  255. * @data: Pointer to the page data
  256. * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
  257. *
  258. * This function retrieves the Hardware ECC data from the controller and returns
  259. * ECC data back to the MTD subsystem.
  260. *
  261. * returns: 0 on success or error value on failure
  262. */
  263. static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
  264. u8 *ecc_code)
  265. {
  266. u32 ecc_value = 0;
  267. u8 ecc_reg, ecc_byte;
  268. u32 ecc_status;
  269. /* Wait till the ECC operation is complete */
  270. ecc_status = zynq_nand_waitfor_ecc_completion();
  271. if (ecc_status < 0) {
  272. printf("%s: Timeout\n", __func__);
  273. return ecc_status;
  274. }
  275. for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
  276. /* Read ECC value for each block */
  277. ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
  278. /* Get the ecc status from ecc read value */
  279. ecc_status = (ecc_value >> 24) & 0xFF;
  280. /* ECC value valid */
  281. if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
  282. for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
  283. /* Copy ECC bytes to MTD buffer */
  284. *ecc_code = ecc_value & 0xFF;
  285. ecc_value = ecc_value >> 8;
  286. ecc_code++;
  287. }
  288. } else {
  289. debug("%s: ecc status failed\n", __func__);
  290. }
  291. }
  292. return 0;
  293. }
  294. /*
  295. * onehot - onehot function
  296. * @value: value to check for onehot
  297. *
  298. * This function checks whether a value is onehot or not.
  299. * onehot is if and only if one bit is set.
  300. *
  301. * FIXME: Try to move this in common.h
  302. */
  303. static bool onehot(unsigned short value)
  304. {
  305. bool onehot;
  306. onehot = value && !(value & (value - 1));
  307. return onehot;
  308. }
  309. /*
  310. * zynq_nand_correct_data - ECC correction function
  311. * @mtd: Pointer to the mtd_info structure
  312. * @buf: Pointer to the page data
  313. * @read_ecc: Pointer to the ECC value read from spare data area
  314. * @calc_ecc: Pointer to the calculated ECC value
  315. *
  316. * This function corrects the ECC single bit errors & detects 2-bit errors.
  317. *
  318. * returns: 0 if no ECC errors found
  319. * 1 if single bit error found and corrected.
  320. * -1 if multiple ECC errors found.
  321. */
  322. static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
  323. unsigned char *read_ecc, unsigned char *calc_ecc)
  324. {
  325. unsigned char bit_addr;
  326. unsigned int byte_addr;
  327. unsigned short ecc_odd, ecc_even;
  328. unsigned short read_ecc_lower, read_ecc_upper;
  329. unsigned short calc_ecc_lower, calc_ecc_upper;
  330. read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
  331. read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
  332. calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
  333. calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
  334. ecc_odd = read_ecc_lower ^ calc_ecc_lower;
  335. ecc_even = read_ecc_upper ^ calc_ecc_upper;
  336. if ((ecc_odd == 0) && (ecc_even == 0))
  337. return 0; /* no error */
  338. if (ecc_odd == (~ecc_even & 0xfff)) {
  339. /* bits [11:3] of error code is byte offset */
  340. byte_addr = (ecc_odd >> 3) & 0x1ff;
  341. /* bits [2:0] of error code is bit offset */
  342. bit_addr = ecc_odd & 0x7;
  343. /* Toggling error bit */
  344. buf[byte_addr] ^= (1 << bit_addr);
  345. return 1;
  346. }
  347. if (onehot(ecc_odd | ecc_even))
  348. return 1; /* one error in parity */
  349. return -1; /* Uncorrectable error */
  350. }
  351. /*
  352. * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
  353. * @mtd: mtd info structure
  354. * @chip: nand chip info structure
  355. * @page: page number to read
  356. * @sndcmd: flag whether to issue read command or not
  357. */
  358. static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  359. int page)
  360. {
  361. unsigned long data_phase_addr = 0;
  362. int data_width = 4;
  363. u8 *p;
  364. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  365. p = chip->oob_poi;
  366. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  367. p += mtd->oobsize - data_width;
  368. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  369. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  370. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  371. chip->read_buf(mtd, p, data_width);
  372. return 0;
  373. }
  374. /*
  375. * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
  376. * @mtd: mtd info structure
  377. * @chip: nand chip info structure
  378. * @page: page number to write
  379. */
  380. static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  381. int page)
  382. {
  383. int status = 0, data_width = 4;
  384. const u8 *buf = chip->oob_poi;
  385. unsigned long data_phase_addr = 0;
  386. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  387. chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
  388. buf += mtd->oobsize - data_width;
  389. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  390. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  391. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  392. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  393. chip->write_buf(mtd, buf, data_width);
  394. /* Send command to program the OOB data */
  395. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  396. status = chip->waitfunc(mtd, chip);
  397. return status & NAND_STATUS_FAIL ? -EIO : 0;
  398. }
  399. /*
  400. * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
  401. * @mtd: mtd info structure
  402. * @chip: nand chip info structure
  403. * @buf: buffer to store read data
  404. * @oob_required: must write chip->oob_poi to OOB
  405. * @page: page number to read
  406. */
  407. static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  408. u8 *buf, int oob_required, int page)
  409. {
  410. unsigned long data_width = 4;
  411. unsigned long data_phase_addr = 0;
  412. u8 *p;
  413. chip->read_buf(mtd, buf, mtd->writesize);
  414. p = chip->oob_poi;
  415. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  416. p += (mtd->oobsize - data_width);
  417. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  418. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  419. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  420. chip->read_buf(mtd, p, data_width);
  421. return 0;
  422. }
  423. static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
  424. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  425. {
  426. chip->read_buf(mtd, buf, mtd->writesize);
  427. return 0;
  428. }
  429. static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
  430. struct nand_chip *chip, u32 data_offs,
  431. u32 readlen, u8 *buf, int page)
  432. {
  433. if (data_offs != 0) {
  434. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
  435. buf += data_offs;
  436. }
  437. chip->read_buf(mtd, buf, readlen);
  438. return 0;
  439. }
  440. /*
  441. * zynq_nand_write_page_raw - [Intern] raw page write function
  442. * @mtd: mtd info structure
  443. * @chip: nand chip info structure
  444. * @buf: data buffer
  445. * @oob_required: must write chip->oob_poi to OOB
  446. */
  447. static int zynq_nand_write_page_raw(struct mtd_info *mtd,
  448. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  449. {
  450. unsigned long data_width = 4;
  451. unsigned long data_phase_addr = 0;
  452. u8 *p;
  453. chip->write_buf(mtd, buf, mtd->writesize);
  454. p = chip->oob_poi;
  455. chip->write_buf(mtd, p, (mtd->oobsize - data_width));
  456. p += (mtd->oobsize - data_width);
  457. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  458. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  459. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  460. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  461. chip->write_buf(mtd, p, data_width);
  462. return 0;
  463. }
  464. /*
  465. * nand_write_page_hwecc - Hardware ECC based page write function
  466. * @mtd: Pointer to the mtd info structure
  467. * @chip: Pointer to the NAND chip info structure
  468. * @buf: Pointer to the data buffer
  469. * @oob_required: must write chip->oob_poi to OOB
  470. *
  471. * This functions writes data and hardware generated ECC values in to the page.
  472. */
  473. static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
  474. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  475. {
  476. int i, eccsteps, eccsize = chip->ecc.size;
  477. u8 *ecc_calc = chip->buffers->ecccalc;
  478. const u8 *p = buf;
  479. u32 *eccpos = chip->ecc.layout->eccpos;
  480. unsigned long data_phase_addr = 0;
  481. unsigned long data_width = 4;
  482. u8 *oob_ptr;
  483. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  484. chip->write_buf(mtd, p, eccsize);
  485. p += eccsize;
  486. }
  487. chip->write_buf(mtd, p, (eccsize - data_width));
  488. p += eccsize - data_width;
  489. /* Set ECC Last bit to 1 */
  490. data_phase_addr = (unsigned long) chip->IO_ADDR_W;
  491. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  492. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  493. chip->write_buf(mtd, p, data_width);
  494. /* Wait for ECC to be calculated and read the error values */
  495. p = buf;
  496. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  497. for (i = 0; i < chip->ecc.total; i++)
  498. chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
  499. /* Clear ECC last bit */
  500. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  501. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  502. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  503. /* Write the spare area with ECC bytes */
  504. oob_ptr = chip->oob_poi;
  505. chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  506. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  507. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  508. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  509. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  510. oob_ptr += (mtd->oobsize - data_width);
  511. chip->write_buf(mtd, oob_ptr, data_width);
  512. return 0;
  513. }
  514. /*
  515. * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
  516. * write function
  517. * @mtd: mtd info structure
  518. * @chip: nand chip info structure
  519. * @buf: data buffer
  520. * @oob_required: must write chip->oob_poi to OOB
  521. */
  522. static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
  523. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  524. {
  525. int i, eccsize = chip->ecc.size;
  526. int eccbytes = chip->ecc.bytes;
  527. int eccsteps = chip->ecc.steps;
  528. u8 *ecc_calc = chip->buffers->ecccalc;
  529. const u8 *p = buf;
  530. u32 *eccpos = chip->ecc.layout->eccpos;
  531. /* Software ecc calculation */
  532. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  533. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  534. for (i = 0; i < chip->ecc.total; i++)
  535. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  536. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  537. }
  538. /*
  539. * nand_read_page_hwecc - Hardware ECC based page read function
  540. * @mtd: Pointer to the mtd info structure
  541. * @chip: Pointer to the NAND chip info structure
  542. * @buf: Pointer to the buffer to store read data
  543. * @oob_required: must write chip->oob_poi to OOB
  544. * @page: page number to read
  545. *
  546. * This functions reads data and checks the data integrity by comparing hardware
  547. * generated ECC values and read ECC values from spare area.
  548. *
  549. * returns: 0 always and updates ECC operation status in to MTD structure
  550. */
  551. static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
  552. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  553. {
  554. int i, stat, eccsteps, eccsize = chip->ecc.size;
  555. int eccbytes = chip->ecc.bytes;
  556. u8 *p = buf;
  557. u8 *ecc_calc = chip->buffers->ecccalc;
  558. u8 *ecc_code = chip->buffers->ecccode;
  559. u32 *eccpos = chip->ecc.layout->eccpos;
  560. unsigned long data_phase_addr = 0;
  561. unsigned long data_width = 4;
  562. u8 *oob_ptr;
  563. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  564. chip->read_buf(mtd, p, eccsize);
  565. p += eccsize;
  566. }
  567. chip->read_buf(mtd, p, (eccsize - data_width));
  568. p += eccsize - data_width;
  569. /* Set ECC Last bit to 1 */
  570. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  571. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  572. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  573. chip->read_buf(mtd, p, data_width);
  574. /* Read the calculated ECC value */
  575. p = buf;
  576. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  577. /* Clear ECC last bit */
  578. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  579. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  580. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  581. /* Read the stored ECC value */
  582. oob_ptr = chip->oob_poi;
  583. chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  584. /* de-assert chip select */
  585. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  586. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  587. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  588. oob_ptr += (mtd->oobsize - data_width);
  589. chip->read_buf(mtd, oob_ptr, data_width);
  590. for (i = 0; i < chip->ecc.total; i++)
  591. ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
  592. eccsteps = chip->ecc.steps;
  593. p = buf;
  594. /* Check ECC error for all blocks and correct if it is correctable */
  595. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  596. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  597. if (stat < 0)
  598. mtd->ecc_stats.failed++;
  599. else
  600. mtd->ecc_stats.corrected += stat;
  601. }
  602. return 0;
  603. }
  604. /*
  605. * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
  606. * read function
  607. * @mtd: mtd info structure
  608. * @chip: nand chip info structure
  609. * @buf: buffer to store read data
  610. * @page: page number to read
  611. */
  612. static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
  613. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  614. {
  615. int i, eccsize = chip->ecc.size;
  616. int eccbytes = chip->ecc.bytes;
  617. int eccsteps = chip->ecc.steps;
  618. u8 *p = buf;
  619. u8 *ecc_calc = chip->buffers->ecccalc;
  620. u8 *ecc_code = chip->buffers->ecccode;
  621. u32 *eccpos = chip->ecc.layout->eccpos;
  622. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  623. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  624. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  625. for (i = 0; i < chip->ecc.total; i++)
  626. ecc_code[i] = chip->oob_poi[eccpos[i]];
  627. eccsteps = chip->ecc.steps;
  628. p = buf;
  629. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  630. int stat;
  631. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  632. if (stat < 0)
  633. mtd->ecc_stats.failed++;
  634. else
  635. mtd->ecc_stats.corrected += stat;
  636. }
  637. return 0;
  638. }
  639. /*
  640. * zynq_nand_select_chip - Select the flash device
  641. * @mtd: Pointer to the mtd_info structure
  642. * @chip: Chip number to be selected
  643. *
  644. * This function is empty as the NAND controller handles chip select line
  645. * internally based on the chip address passed in command and data phase.
  646. */
  647. static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
  648. {
  649. /* Not support multiple chips yet */
  650. }
  651. /*
  652. * zynq_nand_cmd_function - Send command to NAND device
  653. * @mtd: Pointer to the mtd_info structure
  654. * @command: The command to be sent to the flash device
  655. * @column: The column address for this command, -1 if none
  656. * @page_addr: The page address for this command, -1 if none
  657. */
  658. static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  659. int column, int page_addr)
  660. {
  661. struct nand_chip *chip = mtd->priv;
  662. const struct zynq_nand_command_format *curr_cmd = NULL;
  663. struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
  664. void *cmd_addr;
  665. unsigned long cmd_data = 0;
  666. unsigned long cmd_phase_addr = 0;
  667. unsigned long data_phase_addr = 0;
  668. u8 end_cmd = 0;
  669. u8 end_cmd_valid = 0;
  670. u32 index;
  671. if (xnand->end_cmd_pending) {
  672. /* Check for end command if this command request is same as the
  673. * pending command then return
  674. */
  675. if (xnand->end_cmd == command) {
  676. xnand->end_cmd = 0;
  677. xnand->end_cmd_pending = 0;
  678. return;
  679. }
  680. }
  681. /* Emulate NAND_CMD_READOOB for large page device */
  682. if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
  683. (command == NAND_CMD_READOOB)) {
  684. column += mtd->writesize;
  685. command = NAND_CMD_READ0;
  686. }
  687. /* Get the command format */
  688. for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
  689. if (command == zynq_nand_commands[index].start_cmd)
  690. break;
  691. if (index == ARRAY_SIZE(zynq_nand_commands)) {
  692. printf("%s: Unsupported start cmd %02x\n", __func__, command);
  693. return;
  694. }
  695. curr_cmd = &zynq_nand_commands[index];
  696. /* Clear interrupt */
  697. writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
  698. /* Get the command phase address */
  699. if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
  700. end_cmd_valid = 1;
  701. if (curr_cmd->end_cmd == NAND_CMD_NONE)
  702. end_cmd = 0x0;
  703. else
  704. end_cmd = curr_cmd->end_cmd;
  705. cmd_phase_addr = (unsigned long)xnand->nand_base |
  706. (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) |
  707. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  708. (COMMAND_PHASE) |
  709. (end_cmd << END_CMD_SHIFT) |
  710. (curr_cmd->start_cmd << START_CMD_SHIFT);
  711. cmd_addr = (void __iomem *)cmd_phase_addr;
  712. /* Get the data phase address */
  713. end_cmd_valid = 0;
  714. data_phase_addr = (unsigned long)xnand->nand_base |
  715. (0x0 << CLEAR_CS_SHIFT) |
  716. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  717. (DATA_PHASE) |
  718. (end_cmd << END_CMD_SHIFT) |
  719. (0x0 << ECC_LAST_SHIFT);
  720. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  721. chip->IO_ADDR_W = chip->IO_ADDR_R;
  722. /* Command phase AXI Read & Write */
  723. if (column != -1 && page_addr != -1) {
  724. /* Adjust columns for 16 bit bus width */
  725. if (chip->options & NAND_BUSWIDTH_16)
  726. column >>= 1;
  727. cmd_data = column;
  728. if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
  729. cmd_data |= page_addr << 16;
  730. /* Another address cycle for devices > 128MiB */
  731. if (chip->chipsize > (128 << 20)) {
  732. writel(cmd_data, cmd_addr);
  733. cmd_data = (page_addr >> 16);
  734. }
  735. } else {
  736. cmd_data |= page_addr << 8;
  737. }
  738. } else if (page_addr != -1) { /* Erase */
  739. cmd_data = page_addr;
  740. } else if (column != -1) { /* Change read/write column, read id etc */
  741. /* Adjust columns for 16 bit bus width */
  742. if ((chip->options & NAND_BUSWIDTH_16) &&
  743. ((command == NAND_CMD_READ0) ||
  744. (command == NAND_CMD_SEQIN) ||
  745. (command == NAND_CMD_RNDOUT) ||
  746. (command == NAND_CMD_RNDIN)))
  747. column >>= 1;
  748. cmd_data = column;
  749. }
  750. writel(cmd_data, cmd_addr);
  751. if (curr_cmd->end_cmd_valid) {
  752. xnand->end_cmd = curr_cmd->end_cmd;
  753. xnand->end_cmd_pending = 1;
  754. }
  755. ndelay(100);
  756. if ((command == NAND_CMD_READ0) ||
  757. (command == NAND_CMD_RESET) ||
  758. (command == NAND_CMD_PARAM) ||
  759. (command == NAND_CMD_GET_FEATURES))
  760. /* wait until command is processed */
  761. nand_wait_ready(mtd);
  762. }
  763. /*
  764. * zynq_nand_read_buf - read chip data into buffer
  765. * @mtd: MTD device structure
  766. * @buf: buffer to store date
  767. * @len: number of bytes to read
  768. */
  769. static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  770. {
  771. struct nand_chip *chip = mtd->priv;
  772. /* Make sure that buf is 32 bit aligned */
  773. if (((unsigned long)buf & 0x3) != 0) {
  774. if (((unsigned long)buf & 0x1) != 0) {
  775. if (len) {
  776. *buf = readb(chip->IO_ADDR_R);
  777. buf += 1;
  778. len--;
  779. }
  780. }
  781. if (((unsigned long)buf & 0x3) != 0) {
  782. if (len >= 2) {
  783. *(u16 *)buf = readw(chip->IO_ADDR_R);
  784. buf += 2;
  785. len -= 2;
  786. }
  787. }
  788. }
  789. /* copy aligned data */
  790. while (len >= 4) {
  791. *(u32 *)buf = readl(chip->IO_ADDR_R);
  792. buf += 4;
  793. len -= 4;
  794. }
  795. /* mop up any remaining bytes */
  796. if (len) {
  797. if (len >= 2) {
  798. *(u16 *)buf = readw(chip->IO_ADDR_R);
  799. buf += 2;
  800. len -= 2;
  801. }
  802. if (len)
  803. *buf = readb(chip->IO_ADDR_R);
  804. }
  805. }
  806. /*
  807. * zynq_nand_write_buf - write buffer to chip
  808. * @mtd: MTD device structure
  809. * @buf: data buffer
  810. * @len: number of bytes to write
  811. */
  812. static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  813. {
  814. struct nand_chip *chip = mtd->priv;
  815. const u32 *nand = chip->IO_ADDR_W;
  816. /* Make sure that buf is 32 bit aligned */
  817. if (((unsigned long)buf & 0x3) != 0) {
  818. if (((unsigned long)buf & 0x1) != 0) {
  819. if (len) {
  820. writeb(*buf, nand);
  821. buf += 1;
  822. len--;
  823. }
  824. }
  825. if (((unsigned long)buf & 0x3) != 0) {
  826. if (len >= 2) {
  827. writew(*(u16 *)buf, nand);
  828. buf += 2;
  829. len -= 2;
  830. }
  831. }
  832. }
  833. /* copy aligned data */
  834. while (len >= 4) {
  835. writel(*(u32 *)buf, nand);
  836. buf += 4;
  837. len -= 4;
  838. }
  839. /* mop up any remaining bytes */
  840. if (len) {
  841. if (len >= 2) {
  842. writew(*(u16 *)buf, nand);
  843. buf += 2;
  844. len -= 2;
  845. }
  846. if (len)
  847. writeb(*buf, nand);
  848. }
  849. }
  850. /*
  851. * zynq_nand_device_ready - Check device ready/busy line
  852. * @mtd: Pointer to the mtd_info structure
  853. *
  854. * returns: 0 on busy or 1 on ready state
  855. */
  856. static int zynq_nand_device_ready(struct mtd_info *mtd)
  857. {
  858. u32 csr_val;
  859. csr_val = readl(&zynq_nand_smc_base->csr);
  860. /* Check the raw_int_status1 bit */
  861. if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
  862. /* Clear the interrupt condition */
  863. writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
  864. return 1;
  865. }
  866. return 0;
  867. }
  868. int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
  869. {
  870. struct zynq_nand_info *xnand;
  871. struct mtd_info *mtd;
  872. unsigned long ecc_page_size;
  873. u8 maf_id, dev_id, i;
  874. u8 get_feature[4];
  875. u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
  876. unsigned long ecc_cfg;
  877. int ondie_ecc_enabled = 0;
  878. int err = -1;
  879. xnand = calloc(1, sizeof(struct zynq_nand_info));
  880. if (!xnand) {
  881. printf("%s: failed to allocate\n", __func__);
  882. goto fail;
  883. }
  884. xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
  885. mtd = get_nand_dev_by_index(0);
  886. nand_chip->priv = xnand;
  887. mtd->priv = nand_chip;
  888. /* Set address of NAND IO lines */
  889. nand_chip->IO_ADDR_R = xnand->nand_base;
  890. nand_chip->IO_ADDR_W = xnand->nand_base;
  891. /* Set the driver entry points for MTD */
  892. nand_chip->cmdfunc = zynq_nand_cmd_function;
  893. nand_chip->dev_ready = zynq_nand_device_ready;
  894. nand_chip->select_chip = zynq_nand_select_chip;
  895. /* If we don't set this delay driver sets 20us by default */
  896. nand_chip->chip_delay = 30;
  897. /* Buffer read/write routines */
  898. nand_chip->read_buf = zynq_nand_read_buf;
  899. nand_chip->write_buf = zynq_nand_write_buf;
  900. nand_chip->bbt_options = NAND_BBT_USE_FLASH;
  901. /* Initialize the NAND flash interface on NAND controller */
  902. if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
  903. printf("%s: nand flash init failed\n", __func__);
  904. goto fail;
  905. }
  906. /* first scan to find the device and get the page size */
  907. if (nand_scan_ident(mtd, 1, NULL)) {
  908. printf("%s: nand_scan_ident failed\n", __func__);
  909. goto fail;
  910. }
  911. /* Send the command for reading device ID */
  912. nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  913. nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  914. /* Read manufacturer and device IDs */
  915. maf_id = nand_chip->read_byte(mtd);
  916. dev_id = nand_chip->read_byte(mtd);
  917. if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
  918. (dev_id == 0xa1) || (dev_id == 0xb1) ||
  919. (dev_id == 0xaa) || (dev_id == 0xba) ||
  920. (dev_id == 0xda) || (dev_id == 0xca) ||
  921. (dev_id == 0xac) || (dev_id == 0xbc) ||
  922. (dev_id == 0xdc) || (dev_id == 0xcc) ||
  923. (dev_id == 0xa3) || (dev_id == 0xb3) ||
  924. (dev_id == 0xd3) || (dev_id == 0xc3))) {
  925. nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
  926. ONDIE_ECC_FEATURE_ADDR, -1);
  927. for (i = 0; i < 4; i++)
  928. writeb(set_feature[i], nand_chip->IO_ADDR_W);
  929. /* Wait for 1us after writing data with SET_FEATURES command */
  930. ndelay(1000);
  931. nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
  932. ONDIE_ECC_FEATURE_ADDR, -1);
  933. nand_chip->read_buf(mtd, get_feature, 4);
  934. if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
  935. debug("%s: OnDie ECC flash\n", __func__);
  936. ondie_ecc_enabled = 1;
  937. } else {
  938. printf("%s: Unable to detect OnDie ECC\n", __func__);
  939. }
  940. }
  941. if (ondie_ecc_enabled) {
  942. /* Bypass the controller ECC block */
  943. ecc_cfg = readl(&zynq_nand_smc_base->emcr);
  944. ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
  945. writel(ecc_cfg, &zynq_nand_smc_base->emcr);
  946. /* The software ECC routines won't work
  947. * with the SMC controller
  948. */
  949. nand_chip->ecc.mode = NAND_ECC_HW;
  950. nand_chip->ecc.strength = 1;
  951. nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
  952. nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
  953. nand_chip->ecc.write_page = zynq_nand_write_page_raw;
  954. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  955. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  956. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  957. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  958. nand_chip->ecc.size = mtd->writesize;
  959. nand_chip->ecc.bytes = 0;
  960. /* NAND with on-die ECC supports subpage reads */
  961. nand_chip->options |= NAND_SUBPAGE_READ;
  962. /* On-Die ECC spare bytes offset 8 is used for ECC codes */
  963. if (ondie_ecc_enabled) {
  964. nand_chip->ecc.layout = &ondie_nand_oob_64;
  965. /* Use the BBT pattern descriptors */
  966. nand_chip->bbt_td = &bbt_main_descr;
  967. nand_chip->bbt_md = &bbt_mirror_descr;
  968. }
  969. } else {
  970. /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
  971. nand_chip->ecc.mode = NAND_ECC_HW;
  972. nand_chip->ecc.strength = 1;
  973. nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
  974. nand_chip->ecc.bytes = 3;
  975. nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
  976. nand_chip->ecc.correct = zynq_nand_correct_data;
  977. nand_chip->ecc.hwctl = NULL;
  978. nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
  979. nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
  980. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  981. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  982. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  983. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  984. switch (mtd->writesize) {
  985. case 512:
  986. ecc_page_size = 0x1;
  987. /* Set the ECC memory config register */
  988. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  989. &zynq_nand_smc_base->emcr);
  990. break;
  991. case 1024:
  992. ecc_page_size = 0x2;
  993. /* Set the ECC memory config register */
  994. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  995. &zynq_nand_smc_base->emcr);
  996. break;
  997. case 2048:
  998. ecc_page_size = 0x3;
  999. /* Set the ECC memory config register */
  1000. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1001. &zynq_nand_smc_base->emcr);
  1002. break;
  1003. default:
  1004. nand_chip->ecc.mode = NAND_ECC_SOFT;
  1005. nand_chip->ecc.calculate = nand_calculate_ecc;
  1006. nand_chip->ecc.correct = nand_correct_data;
  1007. nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
  1008. nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
  1009. nand_chip->ecc.size = 256;
  1010. break;
  1011. }
  1012. if (mtd->oobsize == 16)
  1013. nand_chip->ecc.layout = &nand_oob_16;
  1014. else if (mtd->oobsize == 64)
  1015. nand_chip->ecc.layout = &nand_oob_64;
  1016. else
  1017. printf("%s: No oob layout found\n", __func__);
  1018. }
  1019. /* Second phase scan */
  1020. if (nand_scan_tail(mtd)) {
  1021. printf("%s: nand_scan_tail failed\n", __func__);
  1022. goto fail;
  1023. }
  1024. if (nand_register(devnum, mtd))
  1025. goto fail;
  1026. return 0;
  1027. fail:
  1028. free(xnand);
  1029. return err;
  1030. }
  1031. #ifdef CONFIG_SYS_NAND_SELF_INIT
  1032. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  1033. void __weak board_nand_init(void)
  1034. {
  1035. struct nand_chip *nand = &nand_chip[0];
  1036. if (zynq_nand_init(nand, 0))
  1037. puts("ZYNQ NAND init failed\n");
  1038. }
  1039. #endif