vf610_nfc.c 20 KB

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  1. /*
  2. * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
  3. *
  4. * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
  5. * Ported to U-Boot by Stefan Agner
  6. * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
  7. * Jason ported to M54418TWR and MVFA5.
  8. * Authors: Stefan Agner <stefan.agner@toradex.com>
  9. * Bill Pringlemeir <bpringlemeir@nbsps.com>
  10. * Shaohui Xie <b21989@freescale.com>
  11. * Jason Jin <Jason.jin@freescale.com>
  12. *
  13. * Based on original driver mpc5121_nfc.c.
  14. *
  15. * SPDX-License-Identifier: GPL-2.0+
  16. *
  17. * Limitations:
  18. * - Untested on MPC5125 and M54418.
  19. * - DMA and pipelining not used.
  20. * - 2K pages or less.
  21. * - HW ECC: Only 2K page with 64+ OOB.
  22. * - HW ECC: Only 24 and 32-bit error correction implemented.
  23. */
  24. #include <common.h>
  25. #include <malloc.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/rawnand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <nand.h>
  30. #include <errno.h>
  31. #include <asm/io.h>
  32. /* Register Offsets */
  33. #define NFC_FLASH_CMD1 0x3F00
  34. #define NFC_FLASH_CMD2 0x3F04
  35. #define NFC_COL_ADDR 0x3F08
  36. #define NFC_ROW_ADDR 0x3F0c
  37. #define NFC_ROW_ADDR_INC 0x3F14
  38. #define NFC_FLASH_STATUS1 0x3F18
  39. #define NFC_FLASH_STATUS2 0x3F1c
  40. #define NFC_CACHE_SWAP 0x3F28
  41. #define NFC_SECTOR_SIZE 0x3F2c
  42. #define NFC_FLASH_CONFIG 0x3F30
  43. #define NFC_IRQ_STATUS 0x3F38
  44. /* Addresses for NFC MAIN RAM BUFFER areas */
  45. #define NFC_MAIN_AREA(n) ((n) * 0x1000)
  46. #define PAGE_2K 0x0800
  47. #define OOB_64 0x0040
  48. #define OOB_MAX 0x0100
  49. /*
  50. * NFC_CMD2[CODE] values. See section:
  51. * - 31.4.7 Flash Command Code Description, Vybrid manual
  52. * - 23.8.6 Flash Command Sequencer, MPC5125 manual
  53. *
  54. * Briefly these are bitmasks of controller cycles.
  55. */
  56. #define READ_PAGE_CMD_CODE 0x7EE0
  57. #define READ_ONFI_PARAM_CMD_CODE 0x4860
  58. #define PROGRAM_PAGE_CMD_CODE 0x7FC0
  59. #define ERASE_CMD_CODE 0x4EC0
  60. #define READ_ID_CMD_CODE 0x4804
  61. #define RESET_CMD_CODE 0x4040
  62. #define STATUS_READ_CMD_CODE 0x4068
  63. /* NFC ECC mode define */
  64. #define ECC_BYPASS 0
  65. #define ECC_45_BYTE 6
  66. #define ECC_60_BYTE 7
  67. /*** Register Mask and bit definitions */
  68. /* NFC_FLASH_CMD1 Field */
  69. #define CMD_BYTE2_MASK 0xFF000000
  70. #define CMD_BYTE2_SHIFT 24
  71. /* NFC_FLASH_CM2 Field */
  72. #define CMD_BYTE1_MASK 0xFF000000
  73. #define CMD_BYTE1_SHIFT 24
  74. #define CMD_CODE_MASK 0x00FFFF00
  75. #define CMD_CODE_SHIFT 8
  76. #define BUFNO_MASK 0x00000006
  77. #define BUFNO_SHIFT 1
  78. #define START_BIT (1<<0)
  79. /* NFC_COL_ADDR Field */
  80. #define COL_ADDR_MASK 0x0000FFFF
  81. #define COL_ADDR_SHIFT 0
  82. /* NFC_ROW_ADDR Field */
  83. #define ROW_ADDR_MASK 0x00FFFFFF
  84. #define ROW_ADDR_SHIFT 0
  85. #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
  86. #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
  87. #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
  88. #define ROW_ADDR_CHIP_SEL_SHIFT 24
  89. /* NFC_FLASH_STATUS2 Field */
  90. #define STATUS_BYTE1_MASK 0x000000FF
  91. /* NFC_FLASH_CONFIG Field */
  92. #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
  93. #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
  94. #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
  95. #define CONFIG_DMA_REQ_BIT (1<<20)
  96. #define CONFIG_ECC_MODE_MASK 0x000E0000
  97. #define CONFIG_ECC_MODE_SHIFT 17
  98. #define CONFIG_FAST_FLASH_BIT (1<<16)
  99. #define CONFIG_16BIT (1<<7)
  100. #define CONFIG_BOOT_MODE_BIT (1<<6)
  101. #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
  102. #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
  103. #define CONFIG_PAGE_CNT_MASK 0xF
  104. #define CONFIG_PAGE_CNT_SHIFT 0
  105. /* NFC_IRQ_STATUS Field */
  106. #define IDLE_IRQ_BIT (1<<29)
  107. #define IDLE_EN_BIT (1<<20)
  108. #define CMD_DONE_CLEAR_BIT (1<<18)
  109. #define IDLE_CLEAR_BIT (1<<17)
  110. #define NFC_TIMEOUT (1000)
  111. /*
  112. * ECC status - seems to consume 8 bytes (double word). The documented
  113. * status byte is located in the lowest byte of the second word (which is
  114. * the 4th or 7th byte depending on endianness).
  115. * Calculate an offset to store the ECC status at the end of the buffer.
  116. */
  117. #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
  118. #define ECC_STATUS 0x4
  119. #define ECC_STATUS_MASK 0x80
  120. #define ECC_STATUS_ERR_COUNT 0x3F
  121. enum vf610_nfc_alt_buf {
  122. ALT_BUF_DATA = 0,
  123. ALT_BUF_ID = 1,
  124. ALT_BUF_STAT = 2,
  125. ALT_BUF_ONFI = 3,
  126. };
  127. struct vf610_nfc {
  128. struct nand_chip chip;
  129. void __iomem *regs;
  130. uint buf_offset;
  131. int write_sz;
  132. /* Status and ID are in alternate locations. */
  133. enum vf610_nfc_alt_buf alt_buf;
  134. };
  135. #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
  136. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  137. #define ECC_HW_MODE ECC_45_BYTE
  138. static struct nand_ecclayout vf610_nfc_ecc = {
  139. .eccbytes = 45,
  140. .eccpos = {19, 20, 21, 22, 23,
  141. 24, 25, 26, 27, 28, 29, 30, 31,
  142. 32, 33, 34, 35, 36, 37, 38, 39,
  143. 40, 41, 42, 43, 44, 45, 46, 47,
  144. 48, 49, 50, 51, 52, 53, 54, 55,
  145. 56, 57, 58, 59, 60, 61, 62, 63},
  146. .oobfree = {
  147. {.offset = 2,
  148. .length = 17} }
  149. };
  150. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  151. #define ECC_HW_MODE ECC_60_BYTE
  152. static struct nand_ecclayout vf610_nfc_ecc = {
  153. .eccbytes = 60,
  154. .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
  155. 12, 13, 14, 15, 16, 17, 18, 19,
  156. 20, 21, 22, 23, 24, 25, 26, 27,
  157. 28, 29, 30, 31, 32, 33, 34, 35,
  158. 36, 37, 38, 39, 40, 41, 42, 43,
  159. 44, 45, 46, 47, 48, 49, 50, 51,
  160. 52, 53, 54, 55, 56, 57, 58, 59,
  161. 60, 61, 62, 63 },
  162. .oobfree = {
  163. {.offset = 2,
  164. .length = 2} }
  165. };
  166. #endif
  167. static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
  168. {
  169. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  170. return readl(nfc->regs + reg);
  171. }
  172. static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
  173. {
  174. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  175. writel(val, nfc->regs + reg);
  176. }
  177. static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
  178. {
  179. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
  180. }
  181. static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
  182. {
  183. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
  184. }
  185. static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
  186. u32 mask, u32 shift, u32 val)
  187. {
  188. vf610_nfc_write(mtd, reg,
  189. (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
  190. }
  191. static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
  192. {
  193. /*
  194. * Use this accessor for the internal SRAM buffers. On the ARM
  195. * Freescale Vybrid SoC it's known that the driver can treat
  196. * the SRAM buffer as if it's memory. Other platform might need
  197. * to treat the buffers differently.
  198. *
  199. * For the time being, use memcpy
  200. */
  201. memcpy(dst, src, n);
  202. }
  203. /* Clear flags for upcoming command */
  204. static inline void vf610_nfc_clear_status(void __iomem *regbase)
  205. {
  206. void __iomem *reg = regbase + NFC_IRQ_STATUS;
  207. u32 tmp = __raw_readl(reg);
  208. tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
  209. __raw_writel(tmp, reg);
  210. }
  211. /* Wait for complete operation */
  212. static void vf610_nfc_done(struct mtd_info *mtd)
  213. {
  214. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  215. uint start;
  216. /*
  217. * Barrier is needed after this write. This write need
  218. * to be done before reading the next register the first
  219. * time.
  220. * vf610_nfc_set implicates such a barrier by using writel
  221. * to write to the register.
  222. */
  223. vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
  224. start = get_timer(0);
  225. while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
  226. if (get_timer(start) > NFC_TIMEOUT) {
  227. printf("Timeout while waiting for IDLE.\n");
  228. return;
  229. }
  230. }
  231. vf610_nfc_clear_status(nfc->regs);
  232. }
  233. static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
  234. {
  235. u32 flash_id;
  236. if (col < 4) {
  237. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
  238. flash_id >>= (3 - col) * 8;
  239. } else {
  240. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
  241. flash_id >>= 24;
  242. }
  243. return flash_id & 0xff;
  244. }
  245. static u8 vf610_nfc_get_status(struct mtd_info *mtd)
  246. {
  247. return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
  248. }
  249. /* Single command */
  250. static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
  251. u32 cmd_code)
  252. {
  253. void __iomem *reg = regbase + NFC_FLASH_CMD2;
  254. u32 tmp;
  255. vf610_nfc_clear_status(regbase);
  256. tmp = __raw_readl(reg);
  257. tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
  258. tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
  259. tmp |= cmd_code << CMD_CODE_SHIFT;
  260. __raw_writel(tmp, reg);
  261. }
  262. /* Two commands */
  263. static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
  264. u32 cmd_byte2, u32 cmd_code)
  265. {
  266. void __iomem *reg = regbase + NFC_FLASH_CMD1;
  267. u32 tmp;
  268. vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
  269. tmp = __raw_readl(reg);
  270. tmp &= ~CMD_BYTE2_MASK;
  271. tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
  272. __raw_writel(tmp, reg);
  273. }
  274. static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
  275. {
  276. if (column != -1) {
  277. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  278. if (nfc->chip.options & NAND_BUSWIDTH_16)
  279. column = column / 2;
  280. vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
  281. COL_ADDR_SHIFT, column);
  282. }
  283. if (page != -1)
  284. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  285. ROW_ADDR_SHIFT, page);
  286. }
  287. static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
  288. {
  289. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  290. CONFIG_ECC_MODE_MASK,
  291. CONFIG_ECC_MODE_SHIFT, ecc_mode);
  292. }
  293. static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
  294. {
  295. __raw_writel(size, regbase + NFC_SECTOR_SIZE);
  296. }
  297. /* Send command to NAND chip */
  298. static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
  299. int column, int page)
  300. {
  301. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  302. int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
  303. nfc->buf_offset = max(column, 0);
  304. nfc->alt_buf = ALT_BUF_DATA;
  305. switch (command) {
  306. case NAND_CMD_SEQIN:
  307. /* Use valid column/page from preread... */
  308. vf610_nfc_addr_cycle(mtd, column, page);
  309. nfc->buf_offset = 0;
  310. /*
  311. * SEQIN => data => PAGEPROG sequence is done by the controller
  312. * hence we do not need to issue the command here...
  313. */
  314. return;
  315. case NAND_CMD_PAGEPROG:
  316. trfr_sz += nfc->write_sz;
  317. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  318. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  319. vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
  320. command, PROGRAM_PAGE_CMD_CODE);
  321. break;
  322. case NAND_CMD_RESET:
  323. vf610_nfc_transfer_size(nfc->regs, 0);
  324. vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
  325. break;
  326. case NAND_CMD_READOOB:
  327. trfr_sz += mtd->oobsize;
  328. column = mtd->writesize;
  329. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  330. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  331. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  332. vf610_nfc_addr_cycle(mtd, column, page);
  333. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  334. break;
  335. case NAND_CMD_READ0:
  336. trfr_sz += mtd->writesize + mtd->oobsize;
  337. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  338. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  339. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  340. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  341. vf610_nfc_addr_cycle(mtd, column, page);
  342. break;
  343. case NAND_CMD_PARAM:
  344. nfc->alt_buf = ALT_BUF_ONFI;
  345. trfr_sz = 3 * sizeof(struct nand_onfi_params);
  346. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  347. vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
  348. READ_ONFI_PARAM_CMD_CODE);
  349. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  350. ROW_ADDR_SHIFT, column);
  351. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  352. break;
  353. case NAND_CMD_ERASE1:
  354. vf610_nfc_transfer_size(nfc->regs, 0);
  355. vf610_nfc_send_commands(nfc->regs, command,
  356. NAND_CMD_ERASE2, ERASE_CMD_CODE);
  357. vf610_nfc_addr_cycle(mtd, column, page);
  358. break;
  359. case NAND_CMD_READID:
  360. nfc->alt_buf = ALT_BUF_ID;
  361. nfc->buf_offset = 0;
  362. vf610_nfc_transfer_size(nfc->regs, 0);
  363. vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
  364. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  365. ROW_ADDR_SHIFT, column);
  366. break;
  367. case NAND_CMD_STATUS:
  368. nfc->alt_buf = ALT_BUF_STAT;
  369. vf610_nfc_transfer_size(nfc->regs, 0);
  370. vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
  371. break;
  372. default:
  373. return;
  374. }
  375. vf610_nfc_done(mtd);
  376. nfc->write_sz = 0;
  377. }
  378. /* Read data from NFC buffers */
  379. static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  380. {
  381. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  382. uint c = nfc->buf_offset;
  383. /* Alternate buffers are only supported through read_byte */
  384. if (nfc->alt_buf)
  385. return;
  386. vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
  387. nfc->buf_offset += len;
  388. }
  389. /* Write data to NFC buffers */
  390. static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  391. int len)
  392. {
  393. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  394. uint c = nfc->buf_offset;
  395. uint l;
  396. l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
  397. vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
  398. nfc->write_sz += l;
  399. nfc->buf_offset += l;
  400. }
  401. /* Read byte from NFC buffers */
  402. static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
  403. {
  404. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  405. u8 tmp;
  406. uint c = nfc->buf_offset;
  407. switch (nfc->alt_buf) {
  408. case ALT_BUF_ID:
  409. tmp = vf610_nfc_get_id(mtd, c);
  410. break;
  411. case ALT_BUF_STAT:
  412. tmp = vf610_nfc_get_status(mtd);
  413. break;
  414. #ifdef __LITTLE_ENDIAN
  415. case ALT_BUF_ONFI:
  416. /* Reverse byte since the controller uses big endianness */
  417. c = nfc->buf_offset ^ 0x3;
  418. /* fall-through */
  419. #endif
  420. default:
  421. tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
  422. break;
  423. }
  424. nfc->buf_offset++;
  425. return tmp;
  426. }
  427. /* Read word from NFC buffers */
  428. static u16 vf610_nfc_read_word(struct mtd_info *mtd)
  429. {
  430. u16 tmp;
  431. vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
  432. return tmp;
  433. }
  434. /* If not provided, upper layers apply a fixed delay. */
  435. static int vf610_nfc_dev_ready(struct mtd_info *mtd)
  436. {
  437. /* NFC handles R/B internally; always ready. */
  438. return 1;
  439. }
  440. /*
  441. * This function supports Vybrid only (MPC5125 would have full RB and four CS)
  442. */
  443. static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
  444. {
  445. #ifdef CONFIG_VF610
  446. u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
  447. tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
  448. if (chip >= 0) {
  449. tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
  450. tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
  451. }
  452. vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
  453. #endif
  454. }
  455. /* Count the number of 0's in buff upto max_bits */
  456. static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
  457. {
  458. uint32_t *buff32 = (uint32_t *)buff;
  459. int k, written_bits = 0;
  460. for (k = 0; k < (size / 4); k++) {
  461. written_bits += hweight32(~buff32[k]);
  462. if (written_bits > max_bits)
  463. break;
  464. }
  465. return written_bits;
  466. }
  467. static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
  468. uint8_t *oob, int page)
  469. {
  470. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  471. u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
  472. u8 ecc_status;
  473. u8 ecc_count;
  474. int flips;
  475. int flips_threshold = nfc->chip.ecc.strength / 2;
  476. ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
  477. ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
  478. if (!(ecc_status & ECC_STATUS_MASK))
  479. return ecc_count;
  480. /* Read OOB without ECC unit enabled */
  481. vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
  482. vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
  483. /*
  484. * On an erased page, bit count (including OOB) should be zero or
  485. * at least less then half of the ECC strength.
  486. */
  487. flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
  488. flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
  489. if (unlikely(flips > flips_threshold))
  490. return -EINVAL;
  491. /* Erased page. */
  492. memset(dat, 0xff, nfc->chip.ecc.size);
  493. memset(oob, 0xff, mtd->oobsize);
  494. return flips;
  495. }
  496. static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  497. uint8_t *buf, int oob_required, int page)
  498. {
  499. int eccsize = chip->ecc.size;
  500. int stat;
  501. vf610_nfc_read_buf(mtd, buf, eccsize);
  502. if (oob_required)
  503. vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  504. stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
  505. if (stat < 0) {
  506. mtd->ecc_stats.failed++;
  507. return 0;
  508. } else {
  509. mtd->ecc_stats.corrected += stat;
  510. return stat;
  511. }
  512. }
  513. /*
  514. * ECC will be calculated automatically
  515. */
  516. static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  517. const uint8_t *buf, int oob_required, int page)
  518. {
  519. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  520. vf610_nfc_write_buf(mtd, buf, mtd->writesize);
  521. if (oob_required)
  522. vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  523. /* Always write whole page including OOB due to HW ECC */
  524. nfc->write_sz = mtd->writesize + mtd->oobsize;
  525. return 0;
  526. }
  527. struct vf610_nfc_config {
  528. int hardware_ecc;
  529. int width;
  530. int flash_bbt;
  531. };
  532. static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
  533. {
  534. struct mtd_info *mtd;
  535. struct nand_chip *chip;
  536. struct vf610_nfc *nfc;
  537. int err = 0;
  538. struct vf610_nfc_config cfg = {
  539. .hardware_ecc = 1,
  540. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  541. .width = 16,
  542. #else
  543. .width = 8,
  544. #endif
  545. .flash_bbt = 1,
  546. };
  547. nfc = malloc(sizeof(*nfc));
  548. if (!nfc) {
  549. printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
  550. return -ENOMEM;
  551. }
  552. chip = &nfc->chip;
  553. nfc->regs = addr;
  554. mtd = nand_to_mtd(chip);
  555. nand_set_controller_data(chip, nfc);
  556. if (cfg.width == 16)
  557. chip->options |= NAND_BUSWIDTH_16;
  558. chip->dev_ready = vf610_nfc_dev_ready;
  559. chip->cmdfunc = vf610_nfc_command;
  560. chip->read_byte = vf610_nfc_read_byte;
  561. chip->read_word = vf610_nfc_read_word;
  562. chip->read_buf = vf610_nfc_read_buf;
  563. chip->write_buf = vf610_nfc_write_buf;
  564. chip->select_chip = vf610_nfc_select_chip;
  565. chip->options |= NAND_NO_SUBPAGE_WRITE;
  566. chip->ecc.size = PAGE_2K;
  567. /* Set configuration register. */
  568. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  569. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
  570. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
  571. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
  572. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
  573. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
  574. /* Disable virtual pages, only one elementary transfer unit */
  575. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
  576. CONFIG_PAGE_CNT_SHIFT, 1);
  577. /* first scan to find the device and get the page size */
  578. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
  579. err = -ENXIO;
  580. goto error;
  581. }
  582. if (cfg.width == 16)
  583. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  584. /* Bad block options. */
  585. if (cfg.flash_bbt)
  586. chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
  587. NAND_BBT_CREATE;
  588. /* Single buffer only, max 256 OOB minus ECC status */
  589. if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
  590. dev_err(nfc->dev, "Unsupported flash page size\n");
  591. err = -ENXIO;
  592. goto error;
  593. }
  594. if (cfg.hardware_ecc) {
  595. if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
  596. dev_err(nfc->dev, "Unsupported flash with hwecc\n");
  597. err = -ENXIO;
  598. goto error;
  599. }
  600. if (chip->ecc.size != mtd->writesize) {
  601. dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
  602. dev_err(nfc->dev, "Step size needs to be page size\n");
  603. err = -ENXIO;
  604. goto error;
  605. }
  606. /* Current HW ECC layouts only use 64 bytes of OOB */
  607. if (mtd->oobsize > 64)
  608. mtd->oobsize = 64;
  609. /* propagate ecc.layout to mtd_info */
  610. mtd->ecclayout = chip->ecc.layout;
  611. chip->ecc.read_page = vf610_nfc_read_page;
  612. chip->ecc.write_page = vf610_nfc_write_page;
  613. chip->ecc.mode = NAND_ECC_HW;
  614. chip->ecc.size = PAGE_2K;
  615. chip->ecc.layout = &vf610_nfc_ecc;
  616. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  617. chip->ecc.strength = 24;
  618. chip->ecc.bytes = 45;
  619. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  620. chip->ecc.strength = 32;
  621. chip->ecc.bytes = 60;
  622. #endif
  623. /* Set ECC_STATUS offset */
  624. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  625. CONFIG_ECC_SRAM_ADDR_MASK,
  626. CONFIG_ECC_SRAM_ADDR_SHIFT,
  627. ECC_SRAM_ADDR >> 3);
  628. /* Enable ECC status in SRAM */
  629. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
  630. }
  631. /* second phase scan */
  632. err = nand_scan_tail(mtd);
  633. if (err)
  634. return err;
  635. err = nand_register(devnum, mtd);
  636. if (err)
  637. return err;
  638. return 0;
  639. error:
  640. return err;
  641. }
  642. void board_nand_init(void)
  643. {
  644. int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
  645. if (err)
  646. printf("VF610 NAND init failed (err %d)\n", err);
  647. }