sunxi_nand.c 47 KB

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  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
  3. * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
  4. *
  5. * Derived from:
  6. * https://github.com/yuq/sunxi-nfc-mtd
  7. * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
  8. *
  9. * https://github.com/hno/Allwinner-Info
  10. * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  11. *
  12. * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  13. * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * SPDX-License-Identifier: GPL-2.0+
  26. */
  27. #include <common.h>
  28. #include <fdtdec.h>
  29. #include <memalign.h>
  30. #include <nand.h>
  31. #include <linux/kernel.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/rawnand.h>
  34. #include <linux/mtd/partitions.h>
  35. #include <linux/io.h>
  36. #include <asm/gpio.h>
  37. #include <asm/arch/clock.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #define NFC_REG_CTL 0x0000
  40. #define NFC_REG_ST 0x0004
  41. #define NFC_REG_INT 0x0008
  42. #define NFC_REG_TIMING_CTL 0x000C
  43. #define NFC_REG_TIMING_CFG 0x0010
  44. #define NFC_REG_ADDR_LOW 0x0014
  45. #define NFC_REG_ADDR_HIGH 0x0018
  46. #define NFC_REG_SECTOR_NUM 0x001C
  47. #define NFC_REG_CNT 0x0020
  48. #define NFC_REG_CMD 0x0024
  49. #define NFC_REG_RCMD_SET 0x0028
  50. #define NFC_REG_WCMD_SET 0x002C
  51. #define NFC_REG_IO_DATA 0x0030
  52. #define NFC_REG_ECC_CTL 0x0034
  53. #define NFC_REG_ECC_ST 0x0038
  54. #define NFC_REG_DEBUG 0x003C
  55. #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
  56. #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
  57. #define NFC_REG_SPARE_AREA 0x00A0
  58. #define NFC_REG_PAT_ID 0x00A4
  59. #define NFC_RAM0_BASE 0x0400
  60. #define NFC_RAM1_BASE 0x0800
  61. /* define bit use in NFC_CTL */
  62. #define NFC_EN BIT(0)
  63. #define NFC_RESET BIT(1)
  64. #define NFC_BUS_WIDTH_MSK BIT(2)
  65. #define NFC_BUS_WIDTH_8 (0 << 2)
  66. #define NFC_BUS_WIDTH_16 (1 << 2)
  67. #define NFC_RB_SEL_MSK BIT(3)
  68. #define NFC_RB_SEL(x) ((x) << 3)
  69. #define NFC_CE_SEL_MSK (0x7 << 24)
  70. #define NFC_CE_SEL(x) ((x) << 24)
  71. #define NFC_CE_CTL BIT(6)
  72. #define NFC_PAGE_SHIFT_MSK (0xf << 8)
  73. #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
  74. #define NFC_SAM BIT(12)
  75. #define NFC_RAM_METHOD BIT(14)
  76. #define NFC_DEBUG_CTL BIT(31)
  77. /* define bit use in NFC_ST */
  78. #define NFC_RB_B2R BIT(0)
  79. #define NFC_CMD_INT_FLAG BIT(1)
  80. #define NFC_DMA_INT_FLAG BIT(2)
  81. #define NFC_CMD_FIFO_STATUS BIT(3)
  82. #define NFC_STA BIT(4)
  83. #define NFC_NATCH_INT_FLAG BIT(5)
  84. #define NFC_RB_STATE(x) BIT(x + 8)
  85. /* define bit use in NFC_INT */
  86. #define NFC_B2R_INT_ENABLE BIT(0)
  87. #define NFC_CMD_INT_ENABLE BIT(1)
  88. #define NFC_DMA_INT_ENABLE BIT(2)
  89. #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
  90. NFC_CMD_INT_ENABLE | \
  91. NFC_DMA_INT_ENABLE)
  92. /* define bit use in NFC_TIMING_CTL */
  93. #define NFC_TIMING_CTL_EDO BIT(8)
  94. /* define NFC_TIMING_CFG register layout */
  95. #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
  96. (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
  97. (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
  98. (((tCAD) & 0x7) << 8))
  99. /* define bit use in NFC_CMD */
  100. #define NFC_CMD_LOW_BYTE_MSK 0xff
  101. #define NFC_CMD_HIGH_BYTE_MSK (0xff << 8)
  102. #define NFC_CMD(x) (x)
  103. #define NFC_ADR_NUM_MSK (0x7 << 16)
  104. #define NFC_ADR_NUM(x) (((x) - 1) << 16)
  105. #define NFC_SEND_ADR BIT(19)
  106. #define NFC_ACCESS_DIR BIT(20)
  107. #define NFC_DATA_TRANS BIT(21)
  108. #define NFC_SEND_CMD1 BIT(22)
  109. #define NFC_WAIT_FLAG BIT(23)
  110. #define NFC_SEND_CMD2 BIT(24)
  111. #define NFC_SEQ BIT(25)
  112. #define NFC_DATA_SWAP_METHOD BIT(26)
  113. #define NFC_ROW_AUTO_INC BIT(27)
  114. #define NFC_SEND_CMD3 BIT(28)
  115. #define NFC_SEND_CMD4 BIT(29)
  116. #define NFC_CMD_TYPE_MSK (0x3 << 30)
  117. #define NFC_NORMAL_OP (0 << 30)
  118. #define NFC_ECC_OP (1 << 30)
  119. #define NFC_PAGE_OP (2 << 30)
  120. /* define bit use in NFC_RCMD_SET */
  121. #define NFC_READ_CMD_MSK 0xff
  122. #define NFC_RND_READ_CMD0_MSK (0xff << 8)
  123. #define NFC_RND_READ_CMD1_MSK (0xff << 16)
  124. /* define bit use in NFC_WCMD_SET */
  125. #define NFC_PROGRAM_CMD_MSK 0xff
  126. #define NFC_RND_WRITE_CMD_MSK (0xff << 8)
  127. #define NFC_READ_CMD0_MSK (0xff << 16)
  128. #define NFC_READ_CMD1_MSK (0xff << 24)
  129. /* define bit use in NFC_ECC_CTL */
  130. #define NFC_ECC_EN BIT(0)
  131. #define NFC_ECC_PIPELINE BIT(3)
  132. #define NFC_ECC_EXCEPTION BIT(4)
  133. #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
  134. #define NFC_ECC_BLOCK_512 (1 << 5)
  135. #define NFC_RANDOM_EN BIT(9)
  136. #define NFC_RANDOM_DIRECTION BIT(10)
  137. #define NFC_ECC_MODE_MSK (0xf << 12)
  138. #define NFC_ECC_MODE(x) ((x) << 12)
  139. #define NFC_RANDOM_SEED_MSK (0x7fff << 16)
  140. #define NFC_RANDOM_SEED(x) ((x) << 16)
  141. /* define bit use in NFC_ECC_ST */
  142. #define NFC_ECC_ERR(x) BIT(x)
  143. #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
  144. #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
  145. #define NFC_DEFAULT_TIMEOUT_MS 1000
  146. #define NFC_SRAM_SIZE 1024
  147. #define NFC_MAX_CS 7
  148. /*
  149. * Ready/Busy detection type: describes the Ready/Busy detection modes
  150. *
  151. * @RB_NONE: no external detection available, rely on STATUS command
  152. * and software timeouts
  153. * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
  154. * pin of the NAND flash chip must be connected to one of the
  155. * native NAND R/B pins (those which can be muxed to the NAND
  156. * Controller)
  157. * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
  158. * pin of the NAND flash chip must be connected to a GPIO capable
  159. * pin.
  160. */
  161. enum sunxi_nand_rb_type {
  162. RB_NONE,
  163. RB_NATIVE,
  164. RB_GPIO,
  165. };
  166. /*
  167. * Ready/Busy structure: stores information related to Ready/Busy detection
  168. *
  169. * @type: the Ready/Busy detection mode
  170. * @info: information related to the R/B detection mode. Either a gpio
  171. * id or a native R/B id (those supported by the NAND controller).
  172. */
  173. struct sunxi_nand_rb {
  174. enum sunxi_nand_rb_type type;
  175. union {
  176. struct gpio_desc gpio;
  177. int nativeid;
  178. } info;
  179. };
  180. /*
  181. * Chip Select structure: stores information related to NAND Chip Select
  182. *
  183. * @cs: the NAND CS id used to communicate with a NAND Chip
  184. * @rb: the Ready/Busy description
  185. */
  186. struct sunxi_nand_chip_sel {
  187. u8 cs;
  188. struct sunxi_nand_rb rb;
  189. };
  190. /*
  191. * sunxi HW ECC infos: stores information related to HW ECC support
  192. *
  193. * @mode: the sunxi ECC mode field deduced from ECC requirements
  194. * @layout: the OOB layout depending on the ECC requirements and the
  195. * selected ECC mode
  196. */
  197. struct sunxi_nand_hw_ecc {
  198. int mode;
  199. struct nand_ecclayout layout;
  200. };
  201. /*
  202. * NAND chip structure: stores NAND chip device related information
  203. *
  204. * @node: used to store NAND chips into a list
  205. * @nand: base NAND chip structure
  206. * @mtd: base MTD structure
  207. * @clk_rate: clk_rate required for this NAND chip
  208. * @timing_cfg TIMING_CFG register value for this NAND chip
  209. * @selected: current active CS
  210. * @nsels: number of CS lines required by the NAND chip
  211. * @sels: array of CS lines descriptions
  212. */
  213. struct sunxi_nand_chip {
  214. struct list_head node;
  215. struct nand_chip nand;
  216. unsigned long clk_rate;
  217. u32 timing_cfg;
  218. u32 timing_ctl;
  219. int selected;
  220. int addr_cycles;
  221. u32 addr[2];
  222. int cmd_cycles;
  223. u8 cmd[2];
  224. int nsels;
  225. struct sunxi_nand_chip_sel sels[0];
  226. };
  227. static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
  228. {
  229. return container_of(nand, struct sunxi_nand_chip, nand);
  230. }
  231. /*
  232. * NAND Controller structure: stores sunxi NAND controller information
  233. *
  234. * @controller: base controller structure
  235. * @dev: parent device (used to print error messages)
  236. * @regs: NAND controller registers
  237. * @ahb_clk: NAND Controller AHB clock
  238. * @mod_clk: NAND Controller mod clock
  239. * @assigned_cs: bitmask describing already assigned CS lines
  240. * @clk_rate: NAND controller current clock rate
  241. * @chips: a list containing all the NAND chips attached to
  242. * this NAND controller
  243. * @complete: a completion object used to wait for NAND
  244. * controller events
  245. */
  246. struct sunxi_nfc {
  247. struct nand_hw_control controller;
  248. struct device *dev;
  249. void __iomem *regs;
  250. struct clk *ahb_clk;
  251. struct clk *mod_clk;
  252. unsigned long assigned_cs;
  253. unsigned long clk_rate;
  254. struct list_head chips;
  255. };
  256. static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
  257. {
  258. return container_of(ctrl, struct sunxi_nfc, controller);
  259. }
  260. static void sunxi_nfc_set_clk_rate(unsigned long hz)
  261. {
  262. struct sunxi_ccm_reg *const ccm =
  263. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  264. int div_m, div_n;
  265. div_m = (clock_get_pll6() + hz - 1) / hz;
  266. for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
  267. if (div_m % 2)
  268. div_m++;
  269. div_m >>= 1;
  270. }
  271. if (div_m > 16)
  272. div_m = 16;
  273. /* config mod clock */
  274. writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
  275. CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
  276. &ccm->nand0_clk_cfg);
  277. /* gate on nand clock */
  278. setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
  279. #ifdef CONFIG_MACH_SUN9I
  280. setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
  281. #else
  282. setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
  283. #endif
  284. }
  285. static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
  286. unsigned int timeout_ms)
  287. {
  288. unsigned int timeout_ticks;
  289. u32 time_start, status;
  290. int ret = -ETIMEDOUT;
  291. if (!timeout_ms)
  292. timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
  293. timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
  294. time_start = get_timer(0);
  295. do {
  296. status = readl(nfc->regs + NFC_REG_ST);
  297. if ((status & flags) == flags) {
  298. ret = 0;
  299. break;
  300. }
  301. udelay(1);
  302. } while (get_timer(time_start) < timeout_ticks);
  303. writel(status & flags, nfc->regs + NFC_REG_ST);
  304. return ret;
  305. }
  306. static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
  307. {
  308. unsigned long timeout = (CONFIG_SYS_HZ *
  309. NFC_DEFAULT_TIMEOUT_MS) / 1000;
  310. u32 time_start;
  311. time_start = get_timer(0);
  312. do {
  313. if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
  314. return 0;
  315. } while (get_timer(time_start) < timeout);
  316. dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
  317. return -ETIMEDOUT;
  318. }
  319. static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
  320. {
  321. unsigned long timeout = (CONFIG_SYS_HZ *
  322. NFC_DEFAULT_TIMEOUT_MS) / 1000;
  323. u32 time_start;
  324. writel(0, nfc->regs + NFC_REG_ECC_CTL);
  325. writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
  326. time_start = get_timer(0);
  327. do {
  328. if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
  329. return 0;
  330. } while (get_timer(time_start) < timeout);
  331. dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
  332. return -ETIMEDOUT;
  333. }
  334. static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
  335. {
  336. struct nand_chip *nand = mtd_to_nand(mtd);
  337. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  338. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  339. struct sunxi_nand_rb *rb;
  340. unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
  341. int ret;
  342. if (sunxi_nand->selected < 0)
  343. return 0;
  344. rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
  345. switch (rb->type) {
  346. case RB_NATIVE:
  347. ret = !!(readl(nfc->regs + NFC_REG_ST) &
  348. NFC_RB_STATE(rb->info.nativeid));
  349. if (ret)
  350. break;
  351. sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
  352. ret = !!(readl(nfc->regs + NFC_REG_ST) &
  353. NFC_RB_STATE(rb->info.nativeid));
  354. break;
  355. case RB_GPIO:
  356. ret = dm_gpio_get_value(&rb->info.gpio);
  357. break;
  358. case RB_NONE:
  359. default:
  360. ret = 0;
  361. dev_err(nfc->dev, "cannot check R/B NAND status!\n");
  362. break;
  363. }
  364. return ret;
  365. }
  366. static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
  367. {
  368. struct nand_chip *nand = mtd_to_nand(mtd);
  369. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  370. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  371. struct sunxi_nand_chip_sel *sel;
  372. u32 ctl;
  373. if (chip > 0 && chip >= sunxi_nand->nsels)
  374. return;
  375. if (chip == sunxi_nand->selected)
  376. return;
  377. ctl = readl(nfc->regs + NFC_REG_CTL) &
  378. ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
  379. if (chip >= 0) {
  380. sel = &sunxi_nand->sels[chip];
  381. ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
  382. NFC_PAGE_SHIFT(nand->page_shift - 10);
  383. if (sel->rb.type == RB_NONE) {
  384. nand->dev_ready = NULL;
  385. } else {
  386. nand->dev_ready = sunxi_nfc_dev_ready;
  387. if (sel->rb.type == RB_NATIVE)
  388. ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
  389. }
  390. writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
  391. if (nfc->clk_rate != sunxi_nand->clk_rate) {
  392. sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
  393. nfc->clk_rate = sunxi_nand->clk_rate;
  394. }
  395. }
  396. writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
  397. writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
  398. writel(ctl, nfc->regs + NFC_REG_CTL);
  399. sunxi_nand->selected = chip;
  400. }
  401. static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  402. {
  403. struct nand_chip *nand = mtd_to_nand(mtd);
  404. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  405. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  406. int ret;
  407. int cnt;
  408. int offs = 0;
  409. u32 tmp;
  410. while (len > offs) {
  411. cnt = min(len - offs, NFC_SRAM_SIZE);
  412. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  413. if (ret)
  414. break;
  415. writel(cnt, nfc->regs + NFC_REG_CNT);
  416. tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
  417. writel(tmp, nfc->regs + NFC_REG_CMD);
  418. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  419. if (ret)
  420. break;
  421. if (buf)
  422. memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
  423. cnt);
  424. offs += cnt;
  425. }
  426. }
  427. static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  428. int len)
  429. {
  430. struct nand_chip *nand = mtd_to_nand(mtd);
  431. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  432. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  433. int ret;
  434. int cnt;
  435. int offs = 0;
  436. u32 tmp;
  437. while (len > offs) {
  438. cnt = min(len - offs, NFC_SRAM_SIZE);
  439. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  440. if (ret)
  441. break;
  442. writel(cnt, nfc->regs + NFC_REG_CNT);
  443. memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
  444. tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
  445. NFC_ACCESS_DIR;
  446. writel(tmp, nfc->regs + NFC_REG_CMD);
  447. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  448. if (ret)
  449. break;
  450. offs += cnt;
  451. }
  452. }
  453. static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
  454. {
  455. uint8_t ret;
  456. sunxi_nfc_read_buf(mtd, &ret, 1);
  457. return ret;
  458. }
  459. static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
  460. unsigned int ctrl)
  461. {
  462. struct nand_chip *nand = mtd_to_nand(mtd);
  463. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  464. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  465. int ret;
  466. u32 tmp;
  467. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  468. if (ret)
  469. return;
  470. if (ctrl & NAND_CTRL_CHANGE) {
  471. tmp = readl(nfc->regs + NFC_REG_CTL);
  472. if (ctrl & NAND_NCE)
  473. tmp |= NFC_CE_CTL;
  474. else
  475. tmp &= ~NFC_CE_CTL;
  476. writel(tmp, nfc->regs + NFC_REG_CTL);
  477. }
  478. if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
  479. !(ctrl & (NAND_CLE | NAND_ALE))) {
  480. u32 cmd = 0;
  481. if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
  482. return;
  483. if (sunxi_nand->cmd_cycles--)
  484. cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
  485. if (sunxi_nand->cmd_cycles--) {
  486. cmd |= NFC_SEND_CMD2;
  487. writel(sunxi_nand->cmd[1],
  488. nfc->regs + NFC_REG_RCMD_SET);
  489. }
  490. sunxi_nand->cmd_cycles = 0;
  491. if (sunxi_nand->addr_cycles) {
  492. cmd |= NFC_SEND_ADR |
  493. NFC_ADR_NUM(sunxi_nand->addr_cycles);
  494. writel(sunxi_nand->addr[0],
  495. nfc->regs + NFC_REG_ADDR_LOW);
  496. }
  497. if (sunxi_nand->addr_cycles > 4)
  498. writel(sunxi_nand->addr[1],
  499. nfc->regs + NFC_REG_ADDR_HIGH);
  500. writel(cmd, nfc->regs + NFC_REG_CMD);
  501. sunxi_nand->addr[0] = 0;
  502. sunxi_nand->addr[1] = 0;
  503. sunxi_nand->addr_cycles = 0;
  504. sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  505. }
  506. if (ctrl & NAND_CLE) {
  507. sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
  508. } else if (ctrl & NAND_ALE) {
  509. sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
  510. dat << ((sunxi_nand->addr_cycles % 4) * 8);
  511. sunxi_nand->addr_cycles++;
  512. }
  513. }
  514. /* These seed values have been extracted from Allwinner's BSP */
  515. static const u16 sunxi_nfc_randomizer_page_seeds[] = {
  516. 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
  517. 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
  518. 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
  519. 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
  520. 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
  521. 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
  522. 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
  523. 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
  524. 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
  525. 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
  526. 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
  527. 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
  528. 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
  529. 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
  530. 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
  531. 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
  532. };
  533. /*
  534. * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
  535. * have been generated using
  536. * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
  537. * the randomizer engine does internally before de/scrambling OOB data.
  538. *
  539. * Those tables are statically defined to avoid calculating randomizer state
  540. * at runtime.
  541. */
  542. static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
  543. 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
  544. 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
  545. 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
  546. 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
  547. 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
  548. 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
  549. 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
  550. 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
  551. 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
  552. 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
  553. 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
  554. 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
  555. 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
  556. 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
  557. 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
  558. 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
  559. };
  560. static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
  561. 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
  562. 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
  563. 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
  564. 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
  565. 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
  566. 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
  567. 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
  568. 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
  569. 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
  570. 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
  571. 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
  572. 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
  573. 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
  574. 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
  575. 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
  576. 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
  577. };
  578. static u16 sunxi_nfc_randomizer_step(u16 state, int count)
  579. {
  580. state &= 0x7fff;
  581. /*
  582. * This loop is just a simple implementation of a Fibonacci LFSR using
  583. * the x16 + x15 + 1 polynomial.
  584. */
  585. while (count--)
  586. state = ((state >> 1) |
  587. (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
  588. return state;
  589. }
  590. static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
  591. {
  592. const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
  593. int mod = mtd->erasesize / mtd->writesize;
  594. if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
  595. mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
  596. if (ecc) {
  597. if (mtd->ecc_step_size == 512)
  598. seeds = sunxi_nfc_randomizer_ecc512_seeds;
  599. else
  600. seeds = sunxi_nfc_randomizer_ecc1024_seeds;
  601. }
  602. return seeds[page % mod];
  603. }
  604. static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
  605. int page, bool ecc)
  606. {
  607. struct nand_chip *nand = mtd_to_nand(mtd);
  608. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  609. u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  610. u16 state;
  611. if (!(nand->options & NAND_NEED_SCRAMBLING))
  612. return;
  613. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  614. state = sunxi_nfc_randomizer_state(mtd, page, ecc);
  615. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
  616. writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
  617. }
  618. static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
  619. {
  620. struct nand_chip *nand = mtd_to_nand(mtd);
  621. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  622. if (!(nand->options & NAND_NEED_SCRAMBLING))
  623. return;
  624. writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
  625. nfc->regs + NFC_REG_ECC_CTL);
  626. }
  627. static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
  628. {
  629. struct nand_chip *nand = mtd_to_nand(mtd);
  630. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  631. if (!(nand->options & NAND_NEED_SCRAMBLING))
  632. return;
  633. writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
  634. nfc->regs + NFC_REG_ECC_CTL);
  635. }
  636. static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
  637. {
  638. u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
  639. bbm[0] ^= state;
  640. bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
  641. }
  642. static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
  643. const uint8_t *buf, int len,
  644. bool ecc, int page)
  645. {
  646. sunxi_nfc_randomizer_config(mtd, page, ecc);
  647. sunxi_nfc_randomizer_enable(mtd);
  648. sunxi_nfc_write_buf(mtd, buf, len);
  649. sunxi_nfc_randomizer_disable(mtd);
  650. }
  651. static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
  652. int len, bool ecc, int page)
  653. {
  654. sunxi_nfc_randomizer_config(mtd, page, ecc);
  655. sunxi_nfc_randomizer_enable(mtd);
  656. sunxi_nfc_read_buf(mtd, buf, len);
  657. sunxi_nfc_randomizer_disable(mtd);
  658. }
  659. static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
  660. {
  661. struct nand_chip *nand = mtd_to_nand(mtd);
  662. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  663. struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
  664. u32 ecc_ctl;
  665. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  666. ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
  667. NFC_ECC_BLOCK_SIZE_MSK);
  668. ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
  669. if (nand->ecc.size == 512)
  670. ecc_ctl |= NFC_ECC_BLOCK_512;
  671. writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
  672. }
  673. static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
  674. {
  675. struct nand_chip *nand = mtd_to_nand(mtd);
  676. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  677. writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
  678. nfc->regs + NFC_REG_ECC_CTL);
  679. }
  680. static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
  681. {
  682. buf[0] = user_data;
  683. buf[1] = user_data >> 8;
  684. buf[2] = user_data >> 16;
  685. buf[3] = user_data >> 24;
  686. }
  687. static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
  688. u8 *data, int data_off,
  689. u8 *oob, int oob_off,
  690. int *cur_off,
  691. unsigned int *max_bitflips,
  692. bool bbm, int page)
  693. {
  694. struct nand_chip *nand = mtd_to_nand(mtd);
  695. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  696. struct nand_ecc_ctrl *ecc = &nand->ecc;
  697. int raw_mode = 0;
  698. u32 status;
  699. int ret;
  700. if (*cur_off != data_off)
  701. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
  702. sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
  703. if (data_off + ecc->size != oob_off)
  704. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  705. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  706. if (ret)
  707. return ret;
  708. sunxi_nfc_randomizer_enable(mtd);
  709. writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
  710. nfc->regs + NFC_REG_CMD);
  711. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  712. sunxi_nfc_randomizer_disable(mtd);
  713. if (ret)
  714. return ret;
  715. *cur_off = oob_off + ecc->bytes + 4;
  716. status = readl(nfc->regs + NFC_REG_ECC_ST);
  717. if (status & NFC_ECC_PAT_FOUND(0)) {
  718. u8 pattern = 0xff;
  719. if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
  720. pattern = 0x0;
  721. memset(data, pattern, ecc->size);
  722. memset(oob, pattern, ecc->bytes + 4);
  723. return 1;
  724. }
  725. ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
  726. memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
  727. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  728. sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
  729. if (status & NFC_ECC_ERR(0)) {
  730. /*
  731. * Re-read the data with the randomizer disabled to identify
  732. * bitflips in erased pages.
  733. */
  734. if (nand->options & NAND_NEED_SCRAMBLING) {
  735. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
  736. nand->read_buf(mtd, data, ecc->size);
  737. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  738. nand->read_buf(mtd, oob, ecc->bytes + 4);
  739. }
  740. ret = nand_check_erased_ecc_chunk(data, ecc->size,
  741. oob, ecc->bytes + 4,
  742. NULL, 0, ecc->strength);
  743. if (ret >= 0)
  744. raw_mode = 1;
  745. } else {
  746. /*
  747. * The engine protects 4 bytes of OOB data per chunk.
  748. * Retrieve the corrected OOB bytes.
  749. */
  750. sunxi_nfc_user_data_to_buf(readl(nfc->regs +
  751. NFC_REG_USER_DATA(0)),
  752. oob);
  753. /* De-randomize the Bad Block Marker. */
  754. if (bbm && nand->options & NAND_NEED_SCRAMBLING)
  755. sunxi_nfc_randomize_bbm(mtd, page, oob);
  756. }
  757. if (ret < 0) {
  758. mtd->ecc_stats.failed++;
  759. } else {
  760. mtd->ecc_stats.corrected += ret;
  761. *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
  762. }
  763. return raw_mode;
  764. }
  765. static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
  766. u8 *oob, int *cur_off,
  767. bool randomize, int page)
  768. {
  769. struct nand_chip *nand = mtd_to_nand(mtd);
  770. struct nand_ecc_ctrl *ecc = &nand->ecc;
  771. int offset = ((ecc->bytes + 4) * ecc->steps);
  772. int len = mtd->oobsize - offset;
  773. if (len <= 0)
  774. return;
  775. if (*cur_off != offset)
  776. nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
  777. offset + mtd->writesize, -1);
  778. if (!randomize)
  779. sunxi_nfc_read_buf(mtd, oob + offset, len);
  780. else
  781. sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
  782. false, page);
  783. *cur_off = mtd->oobsize + mtd->writesize;
  784. }
  785. static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
  786. {
  787. return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
  788. }
  789. static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
  790. const u8 *data, int data_off,
  791. const u8 *oob, int oob_off,
  792. int *cur_off, bool bbm,
  793. int page)
  794. {
  795. struct nand_chip *nand = mtd_to_nand(mtd);
  796. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  797. struct nand_ecc_ctrl *ecc = &nand->ecc;
  798. int ret;
  799. if (data_off != *cur_off)
  800. nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
  801. sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
  802. /* Fill OOB data in */
  803. if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
  804. u8 user_data[4];
  805. memcpy(user_data, oob, 4);
  806. sunxi_nfc_randomize_bbm(mtd, page, user_data);
  807. writel(sunxi_nfc_buf_to_user_data(user_data),
  808. nfc->regs + NFC_REG_USER_DATA(0));
  809. } else {
  810. writel(sunxi_nfc_buf_to_user_data(oob),
  811. nfc->regs + NFC_REG_USER_DATA(0));
  812. }
  813. if (data_off + ecc->size != oob_off)
  814. nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
  815. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  816. if (ret)
  817. return ret;
  818. sunxi_nfc_randomizer_enable(mtd);
  819. writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
  820. NFC_ACCESS_DIR | NFC_ECC_OP,
  821. nfc->regs + NFC_REG_CMD);
  822. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  823. sunxi_nfc_randomizer_disable(mtd);
  824. if (ret)
  825. return ret;
  826. *cur_off = oob_off + ecc->bytes + 4;
  827. return 0;
  828. }
  829. static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
  830. u8 *oob, int *cur_off,
  831. int page)
  832. {
  833. struct nand_chip *nand = mtd_to_nand(mtd);
  834. struct nand_ecc_ctrl *ecc = &nand->ecc;
  835. int offset = ((ecc->bytes + 4) * ecc->steps);
  836. int len = mtd->oobsize - offset;
  837. if (len <= 0)
  838. return;
  839. if (*cur_off != offset)
  840. nand->cmdfunc(mtd, NAND_CMD_RNDIN,
  841. offset + mtd->writesize, -1);
  842. sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
  843. *cur_off = mtd->oobsize + mtd->writesize;
  844. }
  845. static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
  846. struct nand_chip *chip, uint8_t *buf,
  847. int oob_required, int page)
  848. {
  849. struct nand_ecc_ctrl *ecc = &chip->ecc;
  850. unsigned int max_bitflips = 0;
  851. int ret, i, cur_off = 0;
  852. bool raw_mode = false;
  853. sunxi_nfc_hw_ecc_enable(mtd);
  854. for (i = 0; i < ecc->steps; i++) {
  855. int data_off = i * ecc->size;
  856. int oob_off = i * (ecc->bytes + 4);
  857. u8 *data = buf + data_off;
  858. u8 *oob = chip->oob_poi + oob_off;
  859. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
  860. oob_off + mtd->writesize,
  861. &cur_off, &max_bitflips,
  862. !i, page);
  863. if (ret < 0)
  864. return ret;
  865. else if (ret)
  866. raw_mode = true;
  867. }
  868. if (oob_required)
  869. sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
  870. !raw_mode, page);
  871. sunxi_nfc_hw_ecc_disable(mtd);
  872. return max_bitflips;
  873. }
  874. static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
  875. struct nand_chip *chip,
  876. uint32_t data_offs, uint32_t readlen,
  877. uint8_t *bufpoi, int page)
  878. {
  879. struct nand_ecc_ctrl *ecc = &chip->ecc;
  880. int ret, i, cur_off = 0;
  881. unsigned int max_bitflips = 0;
  882. sunxi_nfc_hw_ecc_enable(mtd);
  883. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  884. for (i = data_offs / ecc->size;
  885. i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
  886. int data_off = i * ecc->size;
  887. int oob_off = i * (ecc->bytes + 4);
  888. u8 *data = bufpoi + data_off;
  889. u8 *oob = chip->oob_poi + oob_off;
  890. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
  891. oob, oob_off + mtd->writesize,
  892. &cur_off, &max_bitflips, !i, page);
  893. if (ret < 0)
  894. return ret;
  895. }
  896. sunxi_nfc_hw_ecc_disable(mtd);
  897. return max_bitflips;
  898. }
  899. static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
  900. struct nand_chip *chip,
  901. const uint8_t *buf, int oob_required,
  902. int page)
  903. {
  904. struct nand_ecc_ctrl *ecc = &chip->ecc;
  905. int ret, i, cur_off = 0;
  906. sunxi_nfc_hw_ecc_enable(mtd);
  907. for (i = 0; i < ecc->steps; i++) {
  908. int data_off = i * ecc->size;
  909. int oob_off = i * (ecc->bytes + 4);
  910. const u8 *data = buf + data_off;
  911. const u8 *oob = chip->oob_poi + oob_off;
  912. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
  913. oob_off + mtd->writesize,
  914. &cur_off, !i, page);
  915. if (ret)
  916. return ret;
  917. }
  918. if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
  919. sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
  920. &cur_off, page);
  921. sunxi_nfc_hw_ecc_disable(mtd);
  922. return 0;
  923. }
  924. static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
  925. struct nand_chip *chip,
  926. u32 data_offs, u32 data_len,
  927. const u8 *buf, int oob_required,
  928. int page)
  929. {
  930. struct nand_ecc_ctrl *ecc = &chip->ecc;
  931. int ret, i, cur_off = 0;
  932. sunxi_nfc_hw_ecc_enable(mtd);
  933. for (i = data_offs / ecc->size;
  934. i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
  935. int data_off = i * ecc->size;
  936. int oob_off = i * (ecc->bytes + 4);
  937. const u8 *data = buf + data_off;
  938. const u8 *oob = chip->oob_poi + oob_off;
  939. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
  940. oob_off + mtd->writesize,
  941. &cur_off, !i, page);
  942. if (ret)
  943. return ret;
  944. }
  945. sunxi_nfc_hw_ecc_disable(mtd);
  946. return 0;
  947. }
  948. static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
  949. struct nand_chip *chip,
  950. uint8_t *buf, int oob_required,
  951. int page)
  952. {
  953. struct nand_ecc_ctrl *ecc = &chip->ecc;
  954. unsigned int max_bitflips = 0;
  955. int ret, i, cur_off = 0;
  956. bool raw_mode = false;
  957. sunxi_nfc_hw_ecc_enable(mtd);
  958. for (i = 0; i < ecc->steps; i++) {
  959. int data_off = i * (ecc->size + ecc->bytes + 4);
  960. int oob_off = data_off + ecc->size;
  961. u8 *data = buf + (i * ecc->size);
  962. u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
  963. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
  964. oob_off, &cur_off,
  965. &max_bitflips, !i, page);
  966. if (ret < 0)
  967. return ret;
  968. else if (ret)
  969. raw_mode = true;
  970. }
  971. if (oob_required)
  972. sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
  973. !raw_mode, page);
  974. sunxi_nfc_hw_ecc_disable(mtd);
  975. return max_bitflips;
  976. }
  977. static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
  978. struct nand_chip *chip,
  979. const uint8_t *buf,
  980. int oob_required, int page)
  981. {
  982. struct nand_ecc_ctrl *ecc = &chip->ecc;
  983. int ret, i, cur_off = 0;
  984. sunxi_nfc_hw_ecc_enable(mtd);
  985. for (i = 0; i < ecc->steps; i++) {
  986. int data_off = i * (ecc->size + ecc->bytes + 4);
  987. int oob_off = data_off + ecc->size;
  988. const u8 *data = buf + (i * ecc->size);
  989. const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
  990. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
  991. oob, oob_off, &cur_off,
  992. false, page);
  993. if (ret)
  994. return ret;
  995. }
  996. if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
  997. sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
  998. &cur_off, page);
  999. sunxi_nfc_hw_ecc_disable(mtd);
  1000. return 0;
  1001. }
  1002. static const s32 tWB_lut[] = {6, 12, 16, 20};
  1003. static const s32 tRHW_lut[] = {4, 8, 12, 20};
  1004. static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
  1005. u32 clk_period)
  1006. {
  1007. u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
  1008. int i;
  1009. for (i = 0; i < lut_size; i++) {
  1010. if (clk_cycles <= lut[i])
  1011. return i;
  1012. }
  1013. /* Doesn't fit */
  1014. return -EINVAL;
  1015. }
  1016. #define sunxi_nand_lookup_timing(l, p, c) \
  1017. _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
  1018. static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
  1019. const struct nand_sdr_timings *timings)
  1020. {
  1021. u32 min_clk_period = 0;
  1022. s32 tWB, tADL, tWHR, tRHW, tCAD;
  1023. /* T1 <=> tCLS */
  1024. if (timings->tCLS_min > min_clk_period)
  1025. min_clk_period = timings->tCLS_min;
  1026. /* T2 <=> tCLH */
  1027. if (timings->tCLH_min > min_clk_period)
  1028. min_clk_period = timings->tCLH_min;
  1029. /* T3 <=> tCS */
  1030. if (timings->tCS_min > min_clk_period)
  1031. min_clk_period = timings->tCS_min;
  1032. /* T4 <=> tCH */
  1033. if (timings->tCH_min > min_clk_period)
  1034. min_clk_period = timings->tCH_min;
  1035. /* T5 <=> tWP */
  1036. if (timings->tWP_min > min_clk_period)
  1037. min_clk_period = timings->tWP_min;
  1038. /* T6 <=> tWH */
  1039. if (timings->tWH_min > min_clk_period)
  1040. min_clk_period = timings->tWH_min;
  1041. /* T7 <=> tALS */
  1042. if (timings->tALS_min > min_clk_period)
  1043. min_clk_period = timings->tALS_min;
  1044. /* T8 <=> tDS */
  1045. if (timings->tDS_min > min_clk_period)
  1046. min_clk_period = timings->tDS_min;
  1047. /* T9 <=> tDH */
  1048. if (timings->tDH_min > min_clk_period)
  1049. min_clk_period = timings->tDH_min;
  1050. /* T10 <=> tRR */
  1051. if (timings->tRR_min > (min_clk_period * 3))
  1052. min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
  1053. /* T11 <=> tALH */
  1054. if (timings->tALH_min > min_clk_period)
  1055. min_clk_period = timings->tALH_min;
  1056. /* T12 <=> tRP */
  1057. if (timings->tRP_min > min_clk_period)
  1058. min_clk_period = timings->tRP_min;
  1059. /* T13 <=> tREH */
  1060. if (timings->tREH_min > min_clk_period)
  1061. min_clk_period = timings->tREH_min;
  1062. /* T14 <=> tRC */
  1063. if (timings->tRC_min > (min_clk_period * 2))
  1064. min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
  1065. /* T15 <=> tWC */
  1066. if (timings->tWC_min > (min_clk_period * 2))
  1067. min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
  1068. /* T16 - T19 + tCAD */
  1069. tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
  1070. min_clk_period);
  1071. if (tWB < 0) {
  1072. dev_err(nfc->dev, "unsupported tWB\n");
  1073. return tWB;
  1074. }
  1075. tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
  1076. if (tADL > 3) {
  1077. dev_err(nfc->dev, "unsupported tADL\n");
  1078. return -EINVAL;
  1079. }
  1080. tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
  1081. if (tWHR > 3) {
  1082. dev_err(nfc->dev, "unsupported tWHR\n");
  1083. return -EINVAL;
  1084. }
  1085. tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
  1086. min_clk_period);
  1087. if (tRHW < 0) {
  1088. dev_err(nfc->dev, "unsupported tRHW\n");
  1089. return tRHW;
  1090. }
  1091. /*
  1092. * TODO: according to ONFI specs this value only applies for DDR NAND,
  1093. * but Allwinner seems to set this to 0x7. Mimic them for now.
  1094. */
  1095. tCAD = 0x7;
  1096. /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
  1097. chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
  1098. /*
  1099. * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
  1100. * output cycle timings shall be used if the host drives tRC less than
  1101. * 30 ns.
  1102. */
  1103. chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
  1104. /* Convert min_clk_period from picoseconds to nanoseconds */
  1105. min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
  1106. /*
  1107. * Convert min_clk_period into a clk frequency, then get the
  1108. * appropriate rate for the NAND controller IP given this formula
  1109. * (specified in the datasheet):
  1110. * nand clk_rate = min_clk_rate
  1111. */
  1112. chip->clk_rate = 1000000000L / min_clk_period;
  1113. return 0;
  1114. }
  1115. static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
  1116. {
  1117. struct mtd_info *mtd = nand_to_mtd(&chip->nand);
  1118. const struct nand_sdr_timings *timings;
  1119. int ret;
  1120. int mode;
  1121. mode = onfi_get_async_timing_mode(&chip->nand);
  1122. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  1123. mode = chip->nand.onfi_timing_mode_default;
  1124. } else {
  1125. uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
  1126. int i;
  1127. mode = fls(mode) - 1;
  1128. if (mode < 0)
  1129. mode = 0;
  1130. feature[0] = mode;
  1131. for (i = 0; i < chip->nsels; i++) {
  1132. chip->nand.select_chip(mtd, i);
  1133. ret = chip->nand.onfi_set_features(mtd,
  1134. &chip->nand,
  1135. ONFI_FEATURE_ADDR_TIMING_MODE,
  1136. feature);
  1137. chip->nand.select_chip(mtd, -1);
  1138. if (ret)
  1139. return ret;
  1140. }
  1141. }
  1142. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  1143. if (IS_ERR(timings))
  1144. return PTR_ERR(timings);
  1145. return sunxi_nand_chip_set_timings(chip, timings);
  1146. }
  1147. static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
  1148. struct nand_ecc_ctrl *ecc)
  1149. {
  1150. static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
  1151. struct sunxi_nand_hw_ecc *data;
  1152. struct nand_ecclayout *layout;
  1153. int nsectors;
  1154. int ret;
  1155. int i;
  1156. data = kzalloc(sizeof(*data), GFP_KERNEL);
  1157. if (!data)
  1158. return -ENOMEM;
  1159. if (ecc->size != 512 && ecc->size != 1024)
  1160. return -EINVAL;
  1161. /* Prefer 1k ECC chunk over 512 ones */
  1162. if (ecc->size == 512 && mtd->writesize > 512) {
  1163. ecc->size = 1024;
  1164. ecc->strength *= 2;
  1165. }
  1166. /* Add ECC info retrieval from DT */
  1167. for (i = 0; i < ARRAY_SIZE(strengths); i++) {
  1168. if (ecc->strength <= strengths[i])
  1169. break;
  1170. }
  1171. if (i >= ARRAY_SIZE(strengths)) {
  1172. dev_err(nfc->dev, "unsupported strength\n");
  1173. ret = -ENOTSUPP;
  1174. goto err;
  1175. }
  1176. data->mode = i;
  1177. /* HW ECC always request ECC bytes for 1024 bytes blocks */
  1178. ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
  1179. /* HW ECC always work with even numbers of ECC bytes */
  1180. ecc->bytes = ALIGN(ecc->bytes, 2);
  1181. layout = &data->layout;
  1182. nsectors = mtd->writesize / ecc->size;
  1183. if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
  1184. ret = -EINVAL;
  1185. goto err;
  1186. }
  1187. layout->eccbytes = (ecc->bytes * nsectors);
  1188. ecc->layout = layout;
  1189. ecc->priv = data;
  1190. return 0;
  1191. err:
  1192. kfree(data);
  1193. return ret;
  1194. }
  1195. #ifndef __UBOOT__
  1196. static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
  1197. {
  1198. kfree(ecc->priv);
  1199. }
  1200. #endif /* __UBOOT__ */
  1201. static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
  1202. struct nand_ecc_ctrl *ecc)
  1203. {
  1204. struct nand_ecclayout *layout;
  1205. int nsectors;
  1206. int i, j;
  1207. int ret;
  1208. ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
  1209. if (ret)
  1210. return ret;
  1211. ecc->read_page = sunxi_nfc_hw_ecc_read_page;
  1212. ecc->write_page = sunxi_nfc_hw_ecc_write_page;
  1213. ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
  1214. ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
  1215. layout = ecc->layout;
  1216. nsectors = mtd->writesize / ecc->size;
  1217. for (i = 0; i < nsectors; i++) {
  1218. if (i) {
  1219. layout->oobfree[i].offset =
  1220. layout->oobfree[i - 1].offset +
  1221. layout->oobfree[i - 1].length +
  1222. ecc->bytes;
  1223. layout->oobfree[i].length = 4;
  1224. } else {
  1225. /*
  1226. * The first 2 bytes are used for BB markers, hence we
  1227. * only have 2 bytes available in the first user data
  1228. * section.
  1229. */
  1230. layout->oobfree[i].length = 2;
  1231. layout->oobfree[i].offset = 2;
  1232. }
  1233. for (j = 0; j < ecc->bytes; j++)
  1234. layout->eccpos[(ecc->bytes * i) + j] =
  1235. layout->oobfree[i].offset +
  1236. layout->oobfree[i].length + j;
  1237. }
  1238. if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
  1239. layout->oobfree[nsectors].offset =
  1240. layout->oobfree[nsectors - 1].offset +
  1241. layout->oobfree[nsectors - 1].length +
  1242. ecc->bytes;
  1243. layout->oobfree[nsectors].length = mtd->oobsize -
  1244. ((ecc->bytes + 4) * nsectors);
  1245. }
  1246. return 0;
  1247. }
  1248. static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
  1249. struct nand_ecc_ctrl *ecc)
  1250. {
  1251. struct nand_ecclayout *layout;
  1252. int nsectors;
  1253. int i;
  1254. int ret;
  1255. ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
  1256. if (ret)
  1257. return ret;
  1258. ecc->prepad = 4;
  1259. ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
  1260. ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
  1261. layout = ecc->layout;
  1262. nsectors = mtd->writesize / ecc->size;
  1263. for (i = 0; i < (ecc->bytes * nsectors); i++)
  1264. layout->eccpos[i] = i;
  1265. layout->oobfree[0].length = mtd->oobsize - i;
  1266. layout->oobfree[0].offset = i;
  1267. return 0;
  1268. }
  1269. #ifndef __UBOOT__
  1270. static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
  1271. {
  1272. switch (ecc->mode) {
  1273. case NAND_ECC_HW:
  1274. case NAND_ECC_HW_SYNDROME:
  1275. sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
  1276. break;
  1277. case NAND_ECC_NONE:
  1278. kfree(ecc->layout);
  1279. default:
  1280. break;
  1281. }
  1282. }
  1283. #endif /* __UBOOT__ */
  1284. static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
  1285. {
  1286. struct nand_chip *nand = mtd_to_nand(mtd);
  1287. int ret;
  1288. if (!ecc->size) {
  1289. ecc->size = nand->ecc_step_ds;
  1290. ecc->strength = nand->ecc_strength_ds;
  1291. }
  1292. if (!ecc->size || !ecc->strength)
  1293. return -EINVAL;
  1294. switch (ecc->mode) {
  1295. case NAND_ECC_SOFT_BCH:
  1296. break;
  1297. case NAND_ECC_HW:
  1298. ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
  1299. if (ret)
  1300. return ret;
  1301. break;
  1302. case NAND_ECC_HW_SYNDROME:
  1303. ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
  1304. if (ret)
  1305. return ret;
  1306. break;
  1307. case NAND_ECC_NONE:
  1308. ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
  1309. if (!ecc->layout)
  1310. return -ENOMEM;
  1311. ecc->layout->oobfree[0].length = mtd->oobsize;
  1312. case NAND_ECC_SOFT:
  1313. break;
  1314. default:
  1315. return -EINVAL;
  1316. }
  1317. return 0;
  1318. }
  1319. static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
  1320. {
  1321. const struct nand_sdr_timings *timings;
  1322. const void *blob = gd->fdt_blob;
  1323. struct sunxi_nand_chip *chip;
  1324. struct mtd_info *mtd;
  1325. struct nand_chip *nand;
  1326. int nsels;
  1327. int ret;
  1328. int i;
  1329. u32 cs[8], rb[8];
  1330. if (!fdt_getprop(blob, node, "reg", &nsels))
  1331. return -EINVAL;
  1332. nsels /= sizeof(u32);
  1333. if (!nsels || nsels > 8) {
  1334. dev_err(dev, "invalid reg property size\n");
  1335. return -EINVAL;
  1336. }
  1337. chip = kzalloc(sizeof(*chip) +
  1338. (nsels * sizeof(struct sunxi_nand_chip_sel)),
  1339. GFP_KERNEL);
  1340. if (!chip) {
  1341. dev_err(dev, "could not allocate chip\n");
  1342. return -ENOMEM;
  1343. }
  1344. chip->nsels = nsels;
  1345. chip->selected = -1;
  1346. for (i = 0; i < nsels; i++) {
  1347. cs[i] = -1;
  1348. rb[i] = -1;
  1349. }
  1350. ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
  1351. if (ret) {
  1352. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  1353. return ret;
  1354. }
  1355. ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
  1356. nsels);
  1357. if (ret) {
  1358. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  1359. return ret;
  1360. }
  1361. for (i = 0; i < nsels; i++) {
  1362. int tmp = cs[i];
  1363. if (tmp > NFC_MAX_CS) {
  1364. dev_err(dev,
  1365. "invalid reg value: %u (max CS = 7)\n",
  1366. tmp);
  1367. return -EINVAL;
  1368. }
  1369. if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
  1370. dev_err(dev, "CS %d already assigned\n", tmp);
  1371. return -EINVAL;
  1372. }
  1373. chip->sels[i].cs = tmp;
  1374. tmp = rb[i];
  1375. if (tmp >= 0 && tmp < 2) {
  1376. chip->sels[i].rb.type = RB_NATIVE;
  1377. chip->sels[i].rb.info.nativeid = tmp;
  1378. } else {
  1379. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  1380. "rb-gpios", i,
  1381. &chip->sels[i].rb.info.gpio,
  1382. GPIOD_IS_IN);
  1383. if (ret)
  1384. chip->sels[i].rb.type = RB_GPIO;
  1385. else
  1386. chip->sels[i].rb.type = RB_NONE;
  1387. }
  1388. }
  1389. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1390. if (IS_ERR(timings)) {
  1391. ret = PTR_ERR(timings);
  1392. dev_err(dev,
  1393. "could not retrieve timings for ONFI mode 0: %d\n",
  1394. ret);
  1395. return ret;
  1396. }
  1397. ret = sunxi_nand_chip_set_timings(chip, timings);
  1398. if (ret) {
  1399. dev_err(dev, "could not configure chip timings: %d\n", ret);
  1400. return ret;
  1401. }
  1402. nand = &chip->nand;
  1403. /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
  1404. nand->chip_delay = 200;
  1405. nand->controller = &nfc->controller;
  1406. /*
  1407. * Set the ECC mode to the default value in case nothing is specified
  1408. * in the DT.
  1409. */
  1410. nand->ecc.mode = NAND_ECC_HW;
  1411. nand->flash_node = node;
  1412. nand->select_chip = sunxi_nfc_select_chip;
  1413. nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
  1414. nand->read_buf = sunxi_nfc_read_buf;
  1415. nand->write_buf = sunxi_nfc_write_buf;
  1416. nand->read_byte = sunxi_nfc_read_byte;
  1417. mtd = nand_to_mtd(nand);
  1418. ret = nand_scan_ident(mtd, nsels, NULL);
  1419. if (ret)
  1420. return ret;
  1421. if (nand->bbt_options & NAND_BBT_USE_FLASH)
  1422. nand->bbt_options |= NAND_BBT_NO_OOB;
  1423. if (nand->options & NAND_NEED_SCRAMBLING)
  1424. nand->options |= NAND_NO_SUBPAGE_WRITE;
  1425. nand->options |= NAND_SUBPAGE_READ;
  1426. ret = sunxi_nand_chip_init_timings(chip);
  1427. if (ret) {
  1428. dev_err(dev, "could not configure chip timings: %d\n", ret);
  1429. return ret;
  1430. }
  1431. ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
  1432. if (ret) {
  1433. dev_err(dev, "ECC init failed: %d\n", ret);
  1434. return ret;
  1435. }
  1436. ret = nand_scan_tail(mtd);
  1437. if (ret) {
  1438. dev_err(dev, "nand_scan_tail failed: %d\n", ret);
  1439. return ret;
  1440. }
  1441. ret = nand_register(devnum, mtd);
  1442. if (ret) {
  1443. dev_err(dev, "failed to register mtd device: %d\n", ret);
  1444. return ret;
  1445. }
  1446. list_add_tail(&chip->node, &nfc->chips);
  1447. return 0;
  1448. }
  1449. static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
  1450. {
  1451. const void *blob = gd->fdt_blob;
  1452. int nand_node;
  1453. int ret, i = 0;
  1454. for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
  1455. nand_node = fdt_next_subnode(blob, nand_node))
  1456. i++;
  1457. if (i > 8) {
  1458. dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
  1459. return -EINVAL;
  1460. }
  1461. i = 0;
  1462. for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
  1463. nand_node = fdt_next_subnode(blob, nand_node)) {
  1464. ret = sunxi_nand_chip_init(nand_node, nfc, i++);
  1465. if (ret)
  1466. return ret;
  1467. }
  1468. return 0;
  1469. }
  1470. #ifndef __UBOOT__
  1471. static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
  1472. {
  1473. struct sunxi_nand_chip *chip;
  1474. while (!list_empty(&nfc->chips)) {
  1475. chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
  1476. node);
  1477. nand_release(&chip->mtd);
  1478. sunxi_nand_ecc_cleanup(&chip->nand.ecc);
  1479. list_del(&chip->node);
  1480. kfree(chip);
  1481. }
  1482. }
  1483. #endif /* __UBOOT__ */
  1484. void sunxi_nand_init(void)
  1485. {
  1486. const void *blob = gd->fdt_blob;
  1487. struct sunxi_nfc *nfc;
  1488. fdt_addr_t regs;
  1489. int node;
  1490. int ret;
  1491. nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
  1492. if (!nfc)
  1493. return;
  1494. spin_lock_init(&nfc->controller.lock);
  1495. init_waitqueue_head(&nfc->controller.wq);
  1496. INIT_LIST_HEAD(&nfc->chips);
  1497. node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
  1498. if (node < 0) {
  1499. pr_err("unable to find nfc node in device tree\n");
  1500. goto err;
  1501. }
  1502. if (!fdtdec_get_is_enabled(blob, node)) {
  1503. pr_err("nfc disabled in device tree\n");
  1504. goto err;
  1505. }
  1506. regs = fdtdec_get_addr(blob, node, "reg");
  1507. if (regs == FDT_ADDR_T_NONE) {
  1508. pr_err("unable to find nfc address in device tree\n");
  1509. goto err;
  1510. }
  1511. nfc->regs = (void *)regs;
  1512. ret = sunxi_nfc_rst(nfc);
  1513. if (ret)
  1514. goto err;
  1515. ret = sunxi_nand_chips_init(node, nfc);
  1516. if (ret) {
  1517. dev_err(dev, "failed to init nand chips\n");
  1518. goto err;
  1519. }
  1520. return;
  1521. err:
  1522. kfree(nfc);
  1523. }
  1524. MODULE_LICENSE("GPL v2");
  1525. MODULE_AUTHOR("Boris BREZILLON");
  1526. MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");