nand_timings.c 7.4 KB

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  1. /*
  2. * Copyright (C) 2014 Free Electrons
  3. *
  4. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <common.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mtd/rawnand.h>
  14. static const struct nand_data_interface onfi_sdr_timings[] = {
  15. /* Mode 0 */
  16. {
  17. .type = NAND_SDR_IFACE,
  18. .timings.sdr = {
  19. .tCCS_min = 500000,
  20. .tR_max = 200000000,
  21. .tADL_min = 400000,
  22. .tALH_min = 20000,
  23. .tALS_min = 50000,
  24. .tAR_min = 25000,
  25. .tCEA_max = 100000,
  26. .tCEH_min = 20000,
  27. .tCH_min = 20000,
  28. .tCHZ_max = 100000,
  29. .tCLH_min = 20000,
  30. .tCLR_min = 20000,
  31. .tCLS_min = 50000,
  32. .tCOH_min = 0,
  33. .tCS_min = 70000,
  34. .tDH_min = 20000,
  35. .tDS_min = 40000,
  36. .tFEAT_max = 1000000,
  37. .tIR_min = 10000,
  38. .tITC_max = 1000000,
  39. .tRC_min = 100000,
  40. .tREA_max = 40000,
  41. .tREH_min = 30000,
  42. .tRHOH_min = 0,
  43. .tRHW_min = 200000,
  44. .tRHZ_max = 200000,
  45. .tRLOH_min = 0,
  46. .tRP_min = 50000,
  47. .tRR_min = 40000,
  48. .tRST_max = 250000000000ULL,
  49. .tWB_max = 200000,
  50. .tWC_min = 100000,
  51. .tWH_min = 30000,
  52. .tWHR_min = 120000,
  53. .tWP_min = 50000,
  54. .tWW_min = 100000,
  55. },
  56. },
  57. /* Mode 1 */
  58. {
  59. .type = NAND_SDR_IFACE,
  60. .timings.sdr = {
  61. .tCCS_min = 500000,
  62. .tR_max = 200000000,
  63. .tADL_min = 400000,
  64. .tALH_min = 10000,
  65. .tALS_min = 25000,
  66. .tAR_min = 10000,
  67. .tCEA_max = 45000,
  68. .tCEH_min = 20000,
  69. .tCH_min = 10000,
  70. .tCHZ_max = 50000,
  71. .tCLH_min = 10000,
  72. .tCLR_min = 10000,
  73. .tCLS_min = 25000,
  74. .tCOH_min = 15000,
  75. .tCS_min = 35000,
  76. .tDH_min = 10000,
  77. .tDS_min = 20000,
  78. .tFEAT_max = 1000000,
  79. .tIR_min = 0,
  80. .tITC_max = 1000000,
  81. .tRC_min = 50000,
  82. .tREA_max = 30000,
  83. .tREH_min = 15000,
  84. .tRHOH_min = 15000,
  85. .tRHW_min = 100000,
  86. .tRHZ_max = 100000,
  87. .tRLOH_min = 0,
  88. .tRP_min = 25000,
  89. .tRR_min = 20000,
  90. .tRST_max = 500000000,
  91. .tWB_max = 100000,
  92. .tWC_min = 45000,
  93. .tWH_min = 15000,
  94. .tWHR_min = 80000,
  95. .tWP_min = 25000,
  96. .tWW_min = 100000,
  97. },
  98. },
  99. /* Mode 2 */
  100. {
  101. .type = NAND_SDR_IFACE,
  102. .timings.sdr = {
  103. .tCCS_min = 500000,
  104. .tR_max = 200000000,
  105. .tADL_min = 400000,
  106. .tALH_min = 10000,
  107. .tALS_min = 15000,
  108. .tAR_min = 10000,
  109. .tCEA_max = 30000,
  110. .tCEH_min = 20000,
  111. .tCH_min = 10000,
  112. .tCHZ_max = 50000,
  113. .tCLH_min = 10000,
  114. .tCLR_min = 10000,
  115. .tCLS_min = 15000,
  116. .tCOH_min = 15000,
  117. .tCS_min = 25000,
  118. .tDH_min = 5000,
  119. .tDS_min = 15000,
  120. .tFEAT_max = 1000000,
  121. .tIR_min = 0,
  122. .tITC_max = 1000000,
  123. .tRC_min = 35000,
  124. .tREA_max = 25000,
  125. .tREH_min = 15000,
  126. .tRHOH_min = 15000,
  127. .tRHW_min = 100000,
  128. .tRHZ_max = 100000,
  129. .tRLOH_min = 0,
  130. .tRR_min = 20000,
  131. .tRST_max = 500000000,
  132. .tWB_max = 100000,
  133. .tRP_min = 17000,
  134. .tWC_min = 35000,
  135. .tWH_min = 15000,
  136. .tWHR_min = 80000,
  137. .tWP_min = 17000,
  138. .tWW_min = 100000,
  139. },
  140. },
  141. /* Mode 3 */
  142. {
  143. .type = NAND_SDR_IFACE,
  144. .timings.sdr = {
  145. .tCCS_min = 500000,
  146. .tR_max = 200000000,
  147. .tADL_min = 400000,
  148. .tALH_min = 5000,
  149. .tALS_min = 10000,
  150. .tAR_min = 10000,
  151. .tCEA_max = 25000,
  152. .tCEH_min = 20000,
  153. .tCH_min = 5000,
  154. .tCHZ_max = 50000,
  155. .tCLH_min = 5000,
  156. .tCLR_min = 10000,
  157. .tCLS_min = 10000,
  158. .tCOH_min = 15000,
  159. .tCS_min = 25000,
  160. .tDH_min = 5000,
  161. .tDS_min = 10000,
  162. .tFEAT_max = 1000000,
  163. .tIR_min = 0,
  164. .tITC_max = 1000000,
  165. .tRC_min = 30000,
  166. .tREA_max = 20000,
  167. .tREH_min = 10000,
  168. .tRHOH_min = 15000,
  169. .tRHW_min = 100000,
  170. .tRHZ_max = 100000,
  171. .tRLOH_min = 0,
  172. .tRP_min = 15000,
  173. .tRR_min = 20000,
  174. .tRST_max = 500000000,
  175. .tWB_max = 100000,
  176. .tWC_min = 30000,
  177. .tWH_min = 10000,
  178. .tWHR_min = 80000,
  179. .tWP_min = 15000,
  180. .tWW_min = 100000,
  181. },
  182. },
  183. /* Mode 4 */
  184. {
  185. .type = NAND_SDR_IFACE,
  186. .timings.sdr = {
  187. .tCCS_min = 500000,
  188. .tR_max = 200000000,
  189. .tADL_min = 400000,
  190. .tALH_min = 5000,
  191. .tALS_min = 10000,
  192. .tAR_min = 10000,
  193. .tCEA_max = 25000,
  194. .tCEH_min = 20000,
  195. .tCH_min = 5000,
  196. .tCHZ_max = 30000,
  197. .tCLH_min = 5000,
  198. .tCLR_min = 10000,
  199. .tCLS_min = 10000,
  200. .tCOH_min = 15000,
  201. .tCS_min = 20000,
  202. .tDH_min = 5000,
  203. .tDS_min = 10000,
  204. .tFEAT_max = 1000000,
  205. .tIR_min = 0,
  206. .tITC_max = 1000000,
  207. .tRC_min = 25000,
  208. .tREA_max = 20000,
  209. .tREH_min = 10000,
  210. .tRHOH_min = 15000,
  211. .tRHW_min = 100000,
  212. .tRHZ_max = 100000,
  213. .tRLOH_min = 5000,
  214. .tRP_min = 12000,
  215. .tRR_min = 20000,
  216. .tRST_max = 500000000,
  217. .tWB_max = 100000,
  218. .tWC_min = 25000,
  219. .tWH_min = 10000,
  220. .tWHR_min = 80000,
  221. .tWP_min = 12000,
  222. .tWW_min = 100000,
  223. },
  224. },
  225. /* Mode 5 */
  226. {
  227. .type = NAND_SDR_IFACE,
  228. .timings.sdr = {
  229. .tCCS_min = 500000,
  230. .tR_max = 200000000,
  231. .tADL_min = 400000,
  232. .tALH_min = 5000,
  233. .tALS_min = 10000,
  234. .tAR_min = 10000,
  235. .tCEA_max = 25000,
  236. .tCEH_min = 20000,
  237. .tCH_min = 5000,
  238. .tCHZ_max = 30000,
  239. .tCLH_min = 5000,
  240. .tCLR_min = 10000,
  241. .tCLS_min = 10000,
  242. .tCOH_min = 15000,
  243. .tCS_min = 15000,
  244. .tDH_min = 5000,
  245. .tDS_min = 7000,
  246. .tFEAT_max = 1000000,
  247. .tIR_min = 0,
  248. .tITC_max = 1000000,
  249. .tRC_min = 20000,
  250. .tREA_max = 16000,
  251. .tREH_min = 7000,
  252. .tRHOH_min = 15000,
  253. .tRHW_min = 100000,
  254. .tRHZ_max = 100000,
  255. .tRLOH_min = 5000,
  256. .tRP_min = 10000,
  257. .tRR_min = 20000,
  258. .tRST_max = 500000000,
  259. .tWB_max = 100000,
  260. .tWC_min = 20000,
  261. .tWH_min = 7000,
  262. .tWHR_min = 80000,
  263. .tWP_min = 10000,
  264. .tWW_min = 100000,
  265. },
  266. },
  267. };
  268. /**
  269. * onfi_async_timing_mode_to_sdr_timings - [NAND Interface] Retrieve NAND
  270. * timings according to the given ONFI timing mode
  271. * @mode: ONFI timing mode
  272. */
  273. const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
  274. {
  275. if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
  276. return ERR_PTR(-EINVAL);
  277. return &onfi_sdr_timings[mode].timings.sdr;
  278. }
  279. EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
  280. /**
  281. * onfi_init_data_interface - [NAND Interface] Initialize a data interface from
  282. * given ONFI mode
  283. * @iface: The data interface to be initialized
  284. * @mode: The ONFI timing mode
  285. */
  286. int onfi_init_data_interface(struct nand_chip *chip,
  287. struct nand_data_interface *iface,
  288. enum nand_data_interface_type type,
  289. int timing_mode)
  290. {
  291. if (type != NAND_SDR_IFACE)
  292. return -EINVAL;
  293. if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
  294. return -EINVAL;
  295. *iface = onfi_sdr_timings[timing_mode];
  296. /*
  297. * Initialize timings that cannot be deduced from timing mode:
  298. * tR, tPROG, tCCS, ...
  299. * These information are part of the ONFI parameter page.
  300. */
  301. if (chip->onfi_version) {
  302. struct nand_onfi_params *params = &chip->onfi_params;
  303. struct nand_sdr_timings *timings = &iface->timings.sdr;
  304. /* microseconds -> picoseconds */
  305. timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog);
  306. timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers);
  307. timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r);
  308. /* nanoseconds -> picoseconds */
  309. timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs);
  310. }
  311. return 0;
  312. }
  313. EXPORT_SYMBOL(onfi_init_data_interface);
  314. /**
  315. * nand_get_default_data_interface - [NAND Interface] Retrieve NAND
  316. * data interface for mode 0. This is used as default timing after
  317. * reset.
  318. */
  319. const struct nand_data_interface *nand_get_default_data_interface(void)
  320. {
  321. return &onfi_sdr_timings[0];
  322. }
  323. EXPORT_SYMBOL(nand_get_default_data_interface);