mxs_nand.c 33 KB

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  1. /*
  2. * Freescale i.MX28 NAND flash driver
  3. *
  4. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  5. * on behalf of DENX Software Engineering GmbH
  6. *
  7. * Based on code from LTIB:
  8. * Freescale GPMI NFC NAND Flash Driver
  9. *
  10. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  11. * Copyright (C) 2008 Embedded Alley Solutions, Inc.
  12. *
  13. * SPDX-License-Identifier: GPL-2.0+
  14. */
  15. #include <common.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/rawnand.h>
  18. #include <linux/types.h>
  19. #include <malloc.h>
  20. #include <linux/errno.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/imx-regs.h>
  24. #include <asm/mach-imx/regs-bch.h>
  25. #include <asm/mach-imx/regs-gpmi.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/mach-imx/dma.h>
  28. #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
  29. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
  30. #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
  31. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
  32. #else
  33. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
  34. #endif
  35. #define MXS_NAND_METADATA_SIZE 10
  36. #define MXS_NAND_BITS_PER_ECC_LEVEL 13
  37. #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
  38. #define MXS_NAND_COMMAND_BUFFER_SIZE 32
  39. #else
  40. #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
  41. #endif
  42. #define MXS_NAND_BCH_TIMEOUT 10000
  43. struct mxs_nand_info {
  44. int cur_chip;
  45. uint32_t cmd_queue_len;
  46. uint32_t data_buf_size;
  47. uint8_t *cmd_buf;
  48. uint8_t *data_buf;
  49. uint8_t *oob_buf;
  50. uint8_t marking_block_bad;
  51. uint8_t raw_oob_mode;
  52. /* Functions with altered behaviour */
  53. int (*hooked_read_oob)(struct mtd_info *mtd,
  54. loff_t from, struct mtd_oob_ops *ops);
  55. int (*hooked_write_oob)(struct mtd_info *mtd,
  56. loff_t to, struct mtd_oob_ops *ops);
  57. int (*hooked_block_markbad)(struct mtd_info *mtd,
  58. loff_t ofs);
  59. /* DMA descriptors */
  60. struct mxs_dma_desc **desc;
  61. uint32_t desc_index;
  62. };
  63. struct nand_ecclayout fake_ecc_layout;
  64. static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
  65. static int galois_field = 13;
  66. /*
  67. * Cache management functions
  68. */
  69. #ifndef CONFIG_SYS_DCACHE_OFF
  70. static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
  71. {
  72. uint32_t addr = (uint32_t)info->data_buf;
  73. flush_dcache_range(addr, addr + info->data_buf_size);
  74. }
  75. static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
  76. {
  77. uint32_t addr = (uint32_t)info->data_buf;
  78. invalidate_dcache_range(addr, addr + info->data_buf_size);
  79. }
  80. static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
  81. {
  82. uint32_t addr = (uint32_t)info->cmd_buf;
  83. flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
  84. }
  85. #else
  86. static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
  87. static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
  88. static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
  89. #endif
  90. static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
  91. {
  92. struct mxs_dma_desc *desc;
  93. if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
  94. printf("MXS NAND: Too many DMA descriptors requested\n");
  95. return NULL;
  96. }
  97. desc = info->desc[info->desc_index];
  98. info->desc_index++;
  99. return desc;
  100. }
  101. static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
  102. {
  103. int i;
  104. struct mxs_dma_desc *desc;
  105. for (i = 0; i < info->desc_index; i++) {
  106. desc = info->desc[i];
  107. memset(desc, 0, sizeof(struct mxs_dma_desc));
  108. desc->address = (dma_addr_t)desc;
  109. }
  110. info->desc_index = 0;
  111. }
  112. static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
  113. {
  114. return page_data_size / chunk_data_size;
  115. }
  116. static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
  117. {
  118. return ecc_strength * galois_field;
  119. }
  120. static uint32_t mxs_nand_aux_status_offset(void)
  121. {
  122. return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
  123. }
  124. static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
  125. uint32_t page_oob_size)
  126. {
  127. int ecc_strength;
  128. int max_ecc_strength_supported;
  129. /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
  130. if (is_mx6sx() || is_mx7())
  131. max_ecc_strength_supported = 62;
  132. else
  133. max_ecc_strength_supported = 40;
  134. /*
  135. * Determine the ECC layout with the formula:
  136. * ECC bits per chunk = (total page spare data bits) /
  137. * (bits per ECC level) / (chunks per page)
  138. * where:
  139. * total page spare data bits =
  140. * (page oob size - meta data size) * (bits per byte)
  141. */
  142. ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
  143. / (galois_field *
  144. mxs_nand_ecc_chunk_cnt(page_data_size));
  145. return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
  146. }
  147. static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
  148. uint32_t ecc_strength)
  149. {
  150. uint32_t chunk_data_size_in_bits;
  151. uint32_t chunk_ecc_size_in_bits;
  152. uint32_t chunk_total_size_in_bits;
  153. uint32_t block_mark_chunk_number;
  154. uint32_t block_mark_chunk_bit_offset;
  155. uint32_t block_mark_bit_offset;
  156. chunk_data_size_in_bits = chunk_data_size * 8;
  157. chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
  158. chunk_total_size_in_bits =
  159. chunk_data_size_in_bits + chunk_ecc_size_in_bits;
  160. /* Compute the bit offset of the block mark within the physical page. */
  161. block_mark_bit_offset = page_data_size * 8;
  162. /* Subtract the metadata bits. */
  163. block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
  164. /*
  165. * Compute the chunk number (starting at zero) in which the block mark
  166. * appears.
  167. */
  168. block_mark_chunk_number =
  169. block_mark_bit_offset / chunk_total_size_in_bits;
  170. /*
  171. * Compute the bit offset of the block mark within its chunk, and
  172. * validate it.
  173. */
  174. block_mark_chunk_bit_offset = block_mark_bit_offset -
  175. (block_mark_chunk_number * chunk_total_size_in_bits);
  176. if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
  177. return 1;
  178. /*
  179. * Now that we know the chunk number in which the block mark appears,
  180. * we can subtract all the ECC bits that appear before it.
  181. */
  182. block_mark_bit_offset -=
  183. block_mark_chunk_number * chunk_ecc_size_in_bits;
  184. return block_mark_bit_offset;
  185. }
  186. static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
  187. {
  188. uint32_t ecc_strength;
  189. ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
  190. return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
  191. }
  192. static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
  193. {
  194. uint32_t ecc_strength;
  195. ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
  196. return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
  197. }
  198. /*
  199. * Wait for BCH complete IRQ and clear the IRQ
  200. */
  201. static int mxs_nand_wait_for_bch_complete(void)
  202. {
  203. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  204. int timeout = MXS_NAND_BCH_TIMEOUT;
  205. int ret;
  206. ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
  207. BCH_CTRL_COMPLETE_IRQ, timeout);
  208. writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
  209. return ret;
  210. }
  211. /*
  212. * This is the function that we install in the cmd_ctrl function pointer of the
  213. * owning struct nand_chip. The only functions in the reference implementation
  214. * that use these functions pointers are cmdfunc and select_chip.
  215. *
  216. * In this driver, we implement our own select_chip, so this function will only
  217. * be called by the reference implementation's cmdfunc. For this reason, we can
  218. * ignore the chip enable bit and concentrate only on sending bytes to the NAND
  219. * Flash.
  220. */
  221. static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
  222. {
  223. struct nand_chip *nand = mtd_to_nand(mtd);
  224. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  225. struct mxs_dma_desc *d;
  226. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  227. int ret;
  228. /*
  229. * If this condition is true, something is _VERY_ wrong in MTD
  230. * subsystem!
  231. */
  232. if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
  233. printf("MXS NAND: Command queue too long\n");
  234. return;
  235. }
  236. /*
  237. * Every operation begins with a command byte and a series of zero or
  238. * more address bytes. These are distinguished by either the Address
  239. * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
  240. * asserted. When MTD is ready to execute the command, it will
  241. * deasert both latch enables.
  242. *
  243. * Rather than run a separate DMA operation for every single byte, we
  244. * queue them up and run a single DMA operation for the entire series
  245. * of command and data bytes.
  246. */
  247. if (ctrl & (NAND_ALE | NAND_CLE)) {
  248. if (data != NAND_CMD_NONE)
  249. nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
  250. return;
  251. }
  252. /*
  253. * If control arrives here, MTD has deasserted both the ALE and CLE,
  254. * which means it's ready to run an operation. Check if we have any
  255. * bytes to send.
  256. */
  257. if (nand_info->cmd_queue_len == 0)
  258. return;
  259. /* Compile the DMA descriptor -- a descriptor that sends command. */
  260. d = mxs_nand_get_dma_desc(nand_info);
  261. d->cmd.data =
  262. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  263. MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
  264. MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  265. (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
  266. d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
  267. d->cmd.pio_words[0] =
  268. GPMI_CTRL0_COMMAND_MODE_WRITE |
  269. GPMI_CTRL0_WORD_LENGTH |
  270. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  271. GPMI_CTRL0_ADDRESS_NAND_CLE |
  272. GPMI_CTRL0_ADDRESS_INCREMENT |
  273. nand_info->cmd_queue_len;
  274. mxs_dma_desc_append(channel, d);
  275. /* Flush caches */
  276. mxs_nand_flush_cmd_buf(nand_info);
  277. /* Execute the DMA chain. */
  278. ret = mxs_dma_go(channel);
  279. if (ret)
  280. printf("MXS NAND: Error sending command\n");
  281. mxs_nand_return_dma_descs(nand_info);
  282. /* Reset the command queue. */
  283. nand_info->cmd_queue_len = 0;
  284. }
  285. /*
  286. * Test if the NAND flash is ready.
  287. */
  288. static int mxs_nand_device_ready(struct mtd_info *mtd)
  289. {
  290. struct nand_chip *chip = mtd_to_nand(mtd);
  291. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  292. struct mxs_gpmi_regs *gpmi_regs =
  293. (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  294. uint32_t tmp;
  295. tmp = readl(&gpmi_regs->hw_gpmi_stat);
  296. tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
  297. return tmp & 1;
  298. }
  299. /*
  300. * Select the NAND chip.
  301. */
  302. static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
  303. {
  304. struct nand_chip *nand = mtd_to_nand(mtd);
  305. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  306. nand_info->cur_chip = chip;
  307. }
  308. /*
  309. * Handle block mark swapping.
  310. *
  311. * Note that, when this function is called, it doesn't know whether it's
  312. * swapping the block mark, or swapping it *back* -- but it doesn't matter
  313. * because the the operation is the same.
  314. */
  315. static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
  316. uint8_t *data_buf, uint8_t *oob_buf)
  317. {
  318. uint32_t bit_offset;
  319. uint32_t buf_offset;
  320. uint32_t src;
  321. uint32_t dst;
  322. bit_offset = mxs_nand_mark_bit_offset(mtd);
  323. buf_offset = mxs_nand_mark_byte_offset(mtd);
  324. /*
  325. * Get the byte from the data area that overlays the block mark. Since
  326. * the ECC engine applies its own view to the bits in the page, the
  327. * physical block mark won't (in general) appear on a byte boundary in
  328. * the data.
  329. */
  330. src = data_buf[buf_offset] >> bit_offset;
  331. src |= data_buf[buf_offset + 1] << (8 - bit_offset);
  332. dst = oob_buf[0];
  333. oob_buf[0] = src;
  334. data_buf[buf_offset] &= ~(0xff << bit_offset);
  335. data_buf[buf_offset + 1] &= 0xff << bit_offset;
  336. data_buf[buf_offset] |= dst << bit_offset;
  337. data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
  338. }
  339. /*
  340. * Read data from NAND.
  341. */
  342. static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
  343. {
  344. struct nand_chip *nand = mtd_to_nand(mtd);
  345. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  346. struct mxs_dma_desc *d;
  347. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  348. int ret;
  349. if (length > NAND_MAX_PAGESIZE) {
  350. printf("MXS NAND: DMA buffer too big\n");
  351. return;
  352. }
  353. if (!buf) {
  354. printf("MXS NAND: DMA buffer is NULL\n");
  355. return;
  356. }
  357. /* Compile the DMA descriptor - a descriptor that reads data. */
  358. d = mxs_nand_get_dma_desc(nand_info);
  359. d->cmd.data =
  360. MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
  361. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  362. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  363. (length << MXS_DMA_DESC_BYTES_OFFSET);
  364. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  365. d->cmd.pio_words[0] =
  366. GPMI_CTRL0_COMMAND_MODE_READ |
  367. GPMI_CTRL0_WORD_LENGTH |
  368. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  369. GPMI_CTRL0_ADDRESS_NAND_DATA |
  370. length;
  371. mxs_dma_desc_append(channel, d);
  372. /*
  373. * A DMA descriptor that waits for the command to end and the chip to
  374. * become ready.
  375. *
  376. * I think we actually should *not* be waiting for the chip to become
  377. * ready because, after all, we don't care. I think the original code
  378. * did that and no one has re-thought it yet.
  379. */
  380. d = mxs_nand_get_dma_desc(nand_info);
  381. d->cmd.data =
  382. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  383. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
  384. MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  385. d->cmd.address = 0;
  386. d->cmd.pio_words[0] =
  387. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  388. GPMI_CTRL0_WORD_LENGTH |
  389. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  390. GPMI_CTRL0_ADDRESS_NAND_DATA;
  391. mxs_dma_desc_append(channel, d);
  392. /* Invalidate caches */
  393. mxs_nand_inval_data_buf(nand_info);
  394. /* Execute the DMA chain. */
  395. ret = mxs_dma_go(channel);
  396. if (ret) {
  397. printf("MXS NAND: DMA read error\n");
  398. goto rtn;
  399. }
  400. /* Invalidate caches */
  401. mxs_nand_inval_data_buf(nand_info);
  402. memcpy(buf, nand_info->data_buf, length);
  403. rtn:
  404. mxs_nand_return_dma_descs(nand_info);
  405. }
  406. /*
  407. * Write data to NAND.
  408. */
  409. static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  410. int length)
  411. {
  412. struct nand_chip *nand = mtd_to_nand(mtd);
  413. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  414. struct mxs_dma_desc *d;
  415. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  416. int ret;
  417. if (length > NAND_MAX_PAGESIZE) {
  418. printf("MXS NAND: DMA buffer too big\n");
  419. return;
  420. }
  421. if (!buf) {
  422. printf("MXS NAND: DMA buffer is NULL\n");
  423. return;
  424. }
  425. memcpy(nand_info->data_buf, buf, length);
  426. /* Compile the DMA descriptor - a descriptor that writes data. */
  427. d = mxs_nand_get_dma_desc(nand_info);
  428. d->cmd.data =
  429. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  430. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  431. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  432. (length << MXS_DMA_DESC_BYTES_OFFSET);
  433. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  434. d->cmd.pio_words[0] =
  435. GPMI_CTRL0_COMMAND_MODE_WRITE |
  436. GPMI_CTRL0_WORD_LENGTH |
  437. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  438. GPMI_CTRL0_ADDRESS_NAND_DATA |
  439. length;
  440. mxs_dma_desc_append(channel, d);
  441. /* Flush caches */
  442. mxs_nand_flush_data_buf(nand_info);
  443. /* Execute the DMA chain. */
  444. ret = mxs_dma_go(channel);
  445. if (ret)
  446. printf("MXS NAND: DMA write error\n");
  447. mxs_nand_return_dma_descs(nand_info);
  448. }
  449. /*
  450. * Read a single byte from NAND.
  451. */
  452. static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
  453. {
  454. uint8_t buf;
  455. mxs_nand_read_buf(mtd, &buf, 1);
  456. return buf;
  457. }
  458. /*
  459. * Read a page from NAND.
  460. */
  461. static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
  462. uint8_t *buf, int oob_required,
  463. int page)
  464. {
  465. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  466. struct mxs_dma_desc *d;
  467. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  468. uint32_t corrected = 0, failed = 0;
  469. uint8_t *status;
  470. int i, ret;
  471. /* Compile the DMA descriptor - wait for ready. */
  472. d = mxs_nand_get_dma_desc(nand_info);
  473. d->cmd.data =
  474. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  475. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  476. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  477. d->cmd.address = 0;
  478. d->cmd.pio_words[0] =
  479. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  480. GPMI_CTRL0_WORD_LENGTH |
  481. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  482. GPMI_CTRL0_ADDRESS_NAND_DATA;
  483. mxs_dma_desc_append(channel, d);
  484. /* Compile the DMA descriptor - enable the BCH block and read. */
  485. d = mxs_nand_get_dma_desc(nand_info);
  486. d->cmd.data =
  487. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  488. MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  489. d->cmd.address = 0;
  490. d->cmd.pio_words[0] =
  491. GPMI_CTRL0_COMMAND_MODE_READ |
  492. GPMI_CTRL0_WORD_LENGTH |
  493. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  494. GPMI_CTRL0_ADDRESS_NAND_DATA |
  495. (mtd->writesize + mtd->oobsize);
  496. d->cmd.pio_words[1] = 0;
  497. d->cmd.pio_words[2] =
  498. GPMI_ECCCTRL_ENABLE_ECC |
  499. GPMI_ECCCTRL_ECC_CMD_DECODE |
  500. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  501. d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
  502. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  503. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  504. mxs_dma_desc_append(channel, d);
  505. /* Compile the DMA descriptor - disable the BCH block. */
  506. d = mxs_nand_get_dma_desc(nand_info);
  507. d->cmd.data =
  508. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  509. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  510. (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  511. d->cmd.address = 0;
  512. d->cmd.pio_words[0] =
  513. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  514. GPMI_CTRL0_WORD_LENGTH |
  515. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  516. GPMI_CTRL0_ADDRESS_NAND_DATA |
  517. (mtd->writesize + mtd->oobsize);
  518. d->cmd.pio_words[1] = 0;
  519. d->cmd.pio_words[2] = 0;
  520. mxs_dma_desc_append(channel, d);
  521. /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
  522. d = mxs_nand_get_dma_desc(nand_info);
  523. d->cmd.data =
  524. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  525. MXS_DMA_DESC_DEC_SEM;
  526. d->cmd.address = 0;
  527. mxs_dma_desc_append(channel, d);
  528. /* Invalidate caches */
  529. mxs_nand_inval_data_buf(nand_info);
  530. /* Execute the DMA chain. */
  531. ret = mxs_dma_go(channel);
  532. if (ret) {
  533. printf("MXS NAND: DMA read error\n");
  534. goto rtn;
  535. }
  536. ret = mxs_nand_wait_for_bch_complete();
  537. if (ret) {
  538. printf("MXS NAND: BCH read timeout\n");
  539. goto rtn;
  540. }
  541. /* Invalidate caches */
  542. mxs_nand_inval_data_buf(nand_info);
  543. /* Read DMA completed, now do the mark swapping. */
  544. mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
  545. /* Loop over status bytes, accumulating ECC status. */
  546. status = nand_info->oob_buf + mxs_nand_aux_status_offset();
  547. for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
  548. if (status[i] == 0x00)
  549. continue;
  550. if (status[i] == 0xff)
  551. continue;
  552. if (status[i] == 0xfe) {
  553. failed++;
  554. continue;
  555. }
  556. corrected += status[i];
  557. }
  558. /* Propagate ECC status to the owning MTD. */
  559. mtd->ecc_stats.failed += failed;
  560. mtd->ecc_stats.corrected += corrected;
  561. /*
  562. * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
  563. * details about our policy for delivering the OOB.
  564. *
  565. * We fill the caller's buffer with set bits, and then copy the block
  566. * mark to the caller's buffer. Note that, if block mark swapping was
  567. * necessary, it has already been done, so we can rely on the first
  568. * byte of the auxiliary buffer to contain the block mark.
  569. */
  570. memset(nand->oob_poi, 0xff, mtd->oobsize);
  571. nand->oob_poi[0] = nand_info->oob_buf[0];
  572. memcpy(buf, nand_info->data_buf, mtd->writesize);
  573. rtn:
  574. mxs_nand_return_dma_descs(nand_info);
  575. return ret;
  576. }
  577. /*
  578. * Write a page to NAND.
  579. */
  580. static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
  581. struct nand_chip *nand, const uint8_t *buf,
  582. int oob_required, int page)
  583. {
  584. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  585. struct mxs_dma_desc *d;
  586. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  587. int ret;
  588. memcpy(nand_info->data_buf, buf, mtd->writesize);
  589. memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
  590. /* Handle block mark swapping. */
  591. mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
  592. /* Compile the DMA descriptor - write data. */
  593. d = mxs_nand_get_dma_desc(nand_info);
  594. d->cmd.data =
  595. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  596. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  597. (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  598. d->cmd.address = 0;
  599. d->cmd.pio_words[0] =
  600. GPMI_CTRL0_COMMAND_MODE_WRITE |
  601. GPMI_CTRL0_WORD_LENGTH |
  602. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  603. GPMI_CTRL0_ADDRESS_NAND_DATA;
  604. d->cmd.pio_words[1] = 0;
  605. d->cmd.pio_words[2] =
  606. GPMI_ECCCTRL_ENABLE_ECC |
  607. GPMI_ECCCTRL_ECC_CMD_ENCODE |
  608. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  609. d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
  610. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  611. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  612. mxs_dma_desc_append(channel, d);
  613. /* Flush caches */
  614. mxs_nand_flush_data_buf(nand_info);
  615. /* Execute the DMA chain. */
  616. ret = mxs_dma_go(channel);
  617. if (ret) {
  618. printf("MXS NAND: DMA write error\n");
  619. goto rtn;
  620. }
  621. ret = mxs_nand_wait_for_bch_complete();
  622. if (ret) {
  623. printf("MXS NAND: BCH write timeout\n");
  624. goto rtn;
  625. }
  626. rtn:
  627. mxs_nand_return_dma_descs(nand_info);
  628. return 0;
  629. }
  630. /*
  631. * Read OOB from NAND.
  632. *
  633. * This function is a veneer that replaces the function originally installed by
  634. * the NAND Flash MTD code.
  635. */
  636. static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
  637. struct mtd_oob_ops *ops)
  638. {
  639. struct nand_chip *chip = mtd_to_nand(mtd);
  640. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  641. int ret;
  642. if (ops->mode == MTD_OPS_RAW)
  643. nand_info->raw_oob_mode = 1;
  644. else
  645. nand_info->raw_oob_mode = 0;
  646. ret = nand_info->hooked_read_oob(mtd, from, ops);
  647. nand_info->raw_oob_mode = 0;
  648. return ret;
  649. }
  650. /*
  651. * Write OOB to NAND.
  652. *
  653. * This function is a veneer that replaces the function originally installed by
  654. * the NAND Flash MTD code.
  655. */
  656. static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
  657. struct mtd_oob_ops *ops)
  658. {
  659. struct nand_chip *chip = mtd_to_nand(mtd);
  660. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  661. int ret;
  662. if (ops->mode == MTD_OPS_RAW)
  663. nand_info->raw_oob_mode = 1;
  664. else
  665. nand_info->raw_oob_mode = 0;
  666. ret = nand_info->hooked_write_oob(mtd, to, ops);
  667. nand_info->raw_oob_mode = 0;
  668. return ret;
  669. }
  670. /*
  671. * Mark a block bad in NAND.
  672. *
  673. * This function is a veneer that replaces the function originally installed by
  674. * the NAND Flash MTD code.
  675. */
  676. static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
  677. {
  678. struct nand_chip *chip = mtd_to_nand(mtd);
  679. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  680. int ret;
  681. nand_info->marking_block_bad = 1;
  682. ret = nand_info->hooked_block_markbad(mtd, ofs);
  683. nand_info->marking_block_bad = 0;
  684. return ret;
  685. }
  686. /*
  687. * There are several places in this driver where we have to handle the OOB and
  688. * block marks. This is the function where things are the most complicated, so
  689. * this is where we try to explain it all. All the other places refer back to
  690. * here.
  691. *
  692. * These are the rules, in order of decreasing importance:
  693. *
  694. * 1) Nothing the caller does can be allowed to imperil the block mark, so all
  695. * write operations take measures to protect it.
  696. *
  697. * 2) In read operations, the first byte of the OOB we return must reflect the
  698. * true state of the block mark, no matter where that block mark appears in
  699. * the physical page.
  700. *
  701. * 3) ECC-based read operations return an OOB full of set bits (since we never
  702. * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
  703. * return).
  704. *
  705. * 4) "Raw" read operations return a direct view of the physical bytes in the
  706. * page, using the conventional definition of which bytes are data and which
  707. * are OOB. This gives the caller a way to see the actual, physical bytes
  708. * in the page, without the distortions applied by our ECC engine.
  709. *
  710. * What we do for this specific read operation depends on whether we're doing
  711. * "raw" read, or an ECC-based read.
  712. *
  713. * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
  714. * easy. When reading a page, for example, the NAND Flash MTD code calls our
  715. * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
  716. * ECC-based or raw view of the page is implicit in which function it calls
  717. * (there is a similar pair of ECC-based/raw functions for writing).
  718. *
  719. * Since MTD assumes the OOB is not covered by ECC, there is no pair of
  720. * ECC-based/raw functions for reading or or writing the OOB. The fact that the
  721. * caller wants an ECC-based or raw view of the page is not propagated down to
  722. * this driver.
  723. *
  724. * Since our OOB *is* covered by ECC, we need this information. So, we hook the
  725. * ecc.read_oob and ecc.write_oob function pointers in the owning
  726. * struct mtd_info with our own functions. These hook functions set the
  727. * raw_oob_mode field so that, when control finally arrives here, we'll know
  728. * what to do.
  729. */
  730. static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
  731. int page)
  732. {
  733. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  734. /*
  735. * First, fill in the OOB buffer. If we're doing a raw read, we need to
  736. * get the bytes from the physical page. If we're not doing a raw read,
  737. * we need to fill the buffer with set bits.
  738. */
  739. if (nand_info->raw_oob_mode) {
  740. /*
  741. * If control arrives here, we're doing a "raw" read. Send the
  742. * command to read the conventional OOB and read it.
  743. */
  744. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  745. nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
  746. } else {
  747. /*
  748. * If control arrives here, we're not doing a "raw" read. Fill
  749. * the OOB buffer with set bits and correct the block mark.
  750. */
  751. memset(nand->oob_poi, 0xff, mtd->oobsize);
  752. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  753. mxs_nand_read_buf(mtd, nand->oob_poi, 1);
  754. }
  755. return 0;
  756. }
  757. /*
  758. * Write OOB data to NAND.
  759. */
  760. static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
  761. int page)
  762. {
  763. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  764. uint8_t block_mark = 0;
  765. /*
  766. * There are fundamental incompatibilities between the i.MX GPMI NFC and
  767. * the NAND Flash MTD model that make it essentially impossible to write
  768. * the out-of-band bytes.
  769. *
  770. * We permit *ONE* exception. If the *intent* of writing the OOB is to
  771. * mark a block bad, we can do that.
  772. */
  773. if (!nand_info->marking_block_bad) {
  774. printf("NXS NAND: Writing OOB isn't supported\n");
  775. return -EIO;
  776. }
  777. /* Write the block mark. */
  778. nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  779. nand->write_buf(mtd, &block_mark, 1);
  780. nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  781. /* Check if it worked. */
  782. if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
  783. return -EIO;
  784. return 0;
  785. }
  786. /*
  787. * Claims all blocks are good.
  788. *
  789. * In principle, this function is *only* called when the NAND Flash MTD system
  790. * isn't allowed to keep an in-memory bad block table, so it is forced to ask
  791. * the driver for bad block information.
  792. *
  793. * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
  794. * this function is *only* called when we take it away.
  795. *
  796. * Thus, this function is only called when we want *all* blocks to look good,
  797. * so it *always* return success.
  798. */
  799. static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  800. {
  801. return 0;
  802. }
  803. /*
  804. * Nominally, the purpose of this function is to look for or create the bad
  805. * block table. In fact, since the we call this function at the very end of
  806. * the initialization process started by nand_scan(), and we doesn't have a
  807. * more formal mechanism, we "hook" this function to continue init process.
  808. *
  809. * At this point, the physical NAND Flash chips have been identified and
  810. * counted, so we know the physical geometry. This enables us to make some
  811. * important configuration decisions.
  812. *
  813. * The return value of this function propagates directly back to this driver's
  814. * call to nand_scan(). Anything other than zero will cause this driver to
  815. * tear everything down and declare failure.
  816. */
  817. static int mxs_nand_scan_bbt(struct mtd_info *mtd)
  818. {
  819. struct nand_chip *nand = mtd_to_nand(mtd);
  820. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  821. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  822. uint32_t tmp;
  823. if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
  824. galois_field = 14;
  825. chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
  826. }
  827. if (mtd->oobsize > chunk_data_size) {
  828. printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size);
  829. return -EINVAL;
  830. }
  831. /* Configure BCH and set NFC geometry */
  832. mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  833. /* Configure layout 0 */
  834. tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
  835. << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
  836. tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
  837. tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
  838. << BCH_FLASHLAYOUT0_ECC0_OFFSET;
  839. tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  840. tmp |= (14 == galois_field ? 1 : 0) <<
  841. BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
  842. writel(tmp, &bch_regs->hw_bch_flash0layout0);
  843. tmp = (mtd->writesize + mtd->oobsize)
  844. << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
  845. tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
  846. << BCH_FLASHLAYOUT1_ECCN_OFFSET;
  847. tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  848. tmp |= (14 == galois_field ? 1 : 0) <<
  849. BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
  850. writel(tmp, &bch_regs->hw_bch_flash0layout1);
  851. /* Set *all* chip selects to use layout 0 */
  852. writel(0, &bch_regs->hw_bch_layoutselect);
  853. /* Enable BCH complete interrupt */
  854. writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
  855. /* Hook some operations at the MTD level. */
  856. if (mtd->_read_oob != mxs_nand_hook_read_oob) {
  857. nand_info->hooked_read_oob = mtd->_read_oob;
  858. mtd->_read_oob = mxs_nand_hook_read_oob;
  859. }
  860. if (mtd->_write_oob != mxs_nand_hook_write_oob) {
  861. nand_info->hooked_write_oob = mtd->_write_oob;
  862. mtd->_write_oob = mxs_nand_hook_write_oob;
  863. }
  864. if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
  865. nand_info->hooked_block_markbad = mtd->_block_markbad;
  866. mtd->_block_markbad = mxs_nand_hook_block_markbad;
  867. }
  868. /* We use the reference implementation for bad block management. */
  869. return nand_default_bbt(mtd);
  870. }
  871. /*
  872. * Allocate DMA buffers
  873. */
  874. int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
  875. {
  876. uint8_t *buf;
  877. const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
  878. nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
  879. /* DMA buffers */
  880. buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
  881. if (!buf) {
  882. printf("MXS NAND: Error allocating DMA buffers\n");
  883. return -ENOMEM;
  884. }
  885. memset(buf, 0, nand_info->data_buf_size);
  886. nand_info->data_buf = buf;
  887. nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
  888. /* Command buffers */
  889. nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
  890. MXS_NAND_COMMAND_BUFFER_SIZE);
  891. if (!nand_info->cmd_buf) {
  892. free(buf);
  893. printf("MXS NAND: Error allocating command buffers\n");
  894. return -ENOMEM;
  895. }
  896. memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
  897. nand_info->cmd_queue_len = 0;
  898. return 0;
  899. }
  900. /*
  901. * Initializes the NFC hardware.
  902. */
  903. int mxs_nand_init(struct mxs_nand_info *info)
  904. {
  905. struct mxs_gpmi_regs *gpmi_regs =
  906. (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  907. struct mxs_bch_regs *bch_regs =
  908. (struct mxs_bch_regs *)MXS_BCH_BASE;
  909. int i = 0, j, ret = 0;
  910. info->desc = malloc(sizeof(struct mxs_dma_desc *) *
  911. MXS_NAND_DMA_DESCRIPTOR_COUNT);
  912. if (!info->desc) {
  913. ret = -ENOMEM;
  914. goto err1;
  915. }
  916. /* Allocate the DMA descriptors. */
  917. for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
  918. info->desc[i] = mxs_dma_desc_alloc();
  919. if (!info->desc[i]) {
  920. ret = -ENOMEM;
  921. goto err2;
  922. }
  923. }
  924. /* Init the DMA controller. */
  925. mxs_dma_init();
  926. for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
  927. j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
  928. ret = mxs_dma_init_channel(j);
  929. if (ret)
  930. goto err3;
  931. }
  932. /* Reset the GPMI block. */
  933. mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
  934. mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  935. /*
  936. * Choose NAND mode, set IRQ polarity, disable write protection and
  937. * select BCH ECC.
  938. */
  939. clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
  940. GPMI_CTRL1_GPMI_MODE,
  941. GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
  942. GPMI_CTRL1_BCH_MODE);
  943. return 0;
  944. err3:
  945. for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
  946. mxs_dma_release(j);
  947. err2:
  948. for (--i; i >= 0; i--)
  949. mxs_dma_desc_free(info->desc[i]);
  950. free(info->desc);
  951. err1:
  952. if (ret == -ENOMEM)
  953. printf("MXS NAND: Unable to allocate DMA descriptors\n");
  954. return ret;
  955. }
  956. /*!
  957. * This function is called during the driver binding process.
  958. *
  959. * @param pdev the device structure used to store device specific
  960. * information that is used by the suspend, resume and
  961. * remove functions
  962. *
  963. * @return The function always returns 0.
  964. */
  965. int board_nand_init(struct nand_chip *nand)
  966. {
  967. struct mxs_nand_info *nand_info;
  968. int err;
  969. nand_info = malloc(sizeof(struct mxs_nand_info));
  970. if (!nand_info) {
  971. printf("MXS NAND: Failed to allocate private data\n");
  972. return -ENOMEM;
  973. }
  974. memset(nand_info, 0, sizeof(struct mxs_nand_info));
  975. err = mxs_nand_alloc_buffers(nand_info);
  976. if (err)
  977. goto err1;
  978. err = mxs_nand_init(nand_info);
  979. if (err)
  980. goto err2;
  981. memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
  982. nand_set_controller_data(nand, nand_info);
  983. nand->options |= NAND_NO_SUBPAGE_WRITE;
  984. nand->cmd_ctrl = mxs_nand_cmd_ctrl;
  985. nand->dev_ready = mxs_nand_device_ready;
  986. nand->select_chip = mxs_nand_select_chip;
  987. nand->block_bad = mxs_nand_block_bad;
  988. nand->scan_bbt = mxs_nand_scan_bbt;
  989. nand->read_byte = mxs_nand_read_byte;
  990. nand->read_buf = mxs_nand_read_buf;
  991. nand->write_buf = mxs_nand_write_buf;
  992. nand->ecc.read_page = mxs_nand_ecc_read_page;
  993. nand->ecc.write_page = mxs_nand_ecc_write_page;
  994. nand->ecc.read_oob = mxs_nand_ecc_read_oob;
  995. nand->ecc.write_oob = mxs_nand_ecc_write_oob;
  996. nand->ecc.layout = &fake_ecc_layout;
  997. nand->ecc.mode = NAND_ECC_HW;
  998. nand->ecc.bytes = 9;
  999. nand->ecc.size = 512;
  1000. nand->ecc.strength = 8;
  1001. return 0;
  1002. err2:
  1003. free(nand_info->data_buf);
  1004. free(nand_info->cmd_buf);
  1005. err1:
  1006. free(nand_info);
  1007. return err;
  1008. }