fsl_ifc_spl.c 7.5 KB

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  1. /*
  2. * NAND boot for Freescale Integrated Flash Controller, NAND FCM
  3. *
  4. * Copyright 2011 Freescale Semiconductor, Inc.
  5. * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <fsl_ifc.h>
  12. #include <linux/mtd/rawnand.h>
  13. #ifdef CONFIG_CHAIN_OF_TRUST
  14. #include <fsl_validate.h>
  15. #endif
  16. static inline int is_blank(uchar *addr, int page_size)
  17. {
  18. int i;
  19. for (i = 0; i < page_size; i++) {
  20. if (__raw_readb(&addr[i]) != 0xff)
  21. return 0;
  22. }
  23. /*
  24. * For the SPL, don't worry about uncorrectable errors
  25. * where the main area is all FFs but shouldn't be.
  26. */
  27. return 1;
  28. }
  29. /* returns nonzero if entire page is blank */
  30. static inline int check_read_ecc(uchar *buf, u32 *eccstat,
  31. unsigned int bufnum, int page_size)
  32. {
  33. u32 reg = eccstat[bufnum / 4];
  34. int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
  35. if (errors == 0xf) { /* uncorrectable */
  36. /* Blank pages fail hw ECC checks */
  37. if (is_blank(buf, page_size))
  38. return 1;
  39. puts("ecc error\n");
  40. for (;;)
  41. ;
  42. }
  43. return 0;
  44. }
  45. static inline struct fsl_ifc_runtime *runtime_regs_address(void)
  46. {
  47. struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
  48. int ver = 0;
  49. ver = ifc_in32(&regs.gregs->ifc_rev);
  50. if (ver >= FSL_IFC_V2_0_0)
  51. regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  52. else
  53. regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  54. return regs.rregs;
  55. }
  56. static inline void nand_wait(uchar *buf, int bufnum, int page_size)
  57. {
  58. struct fsl_ifc_runtime *ifc = runtime_regs_address();
  59. u32 status;
  60. u32 eccstat[8];
  61. int bufperpage = page_size / 512;
  62. int bufnum_end, i;
  63. bufnum *= bufperpage;
  64. bufnum_end = bufnum + bufperpage - 1;
  65. do {
  66. status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  67. } while (!(status & IFC_NAND_EVTER_STAT_OPC));
  68. if (status & IFC_NAND_EVTER_STAT_FTOER) {
  69. puts("flash time out error\n");
  70. for (;;)
  71. ;
  72. }
  73. for (i = bufnum / 4; i <= bufnum_end / 4; i++)
  74. eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  75. for (i = bufnum; i <= bufnum_end; i++) {
  76. if (check_read_ecc(buf, eccstat, i, page_size))
  77. break;
  78. }
  79. ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
  80. }
  81. static inline int bad_block(uchar *marker, int port_size)
  82. {
  83. if (port_size == 8)
  84. return __raw_readb(marker) != 0xff;
  85. else
  86. return __raw_readw((u16 *)marker) != 0xffff;
  87. }
  88. int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  89. {
  90. struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
  91. struct fsl_ifc_runtime *ifc = NULL;
  92. uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  93. int page_size;
  94. int port_size;
  95. int pages_per_blk;
  96. int blk_size;
  97. int bad_marker = 0;
  98. int bufnum_mask, bufnum, ver = 0;
  99. int csor, cspr;
  100. int pos = 0;
  101. int j = 0;
  102. int sram_addr;
  103. int pg_no;
  104. uchar *dst = vdst;
  105. ifc = runtime_regs_address();
  106. /* Get NAND Flash configuration */
  107. csor = CONFIG_SYS_NAND_CSOR;
  108. cspr = CONFIG_SYS_NAND_CSPR;
  109. port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
  110. if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
  111. page_size = 8192;
  112. bufnum_mask = 0x0;
  113. } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
  114. page_size = 4096;
  115. bufnum_mask = 0x1;
  116. } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
  117. page_size = 2048;
  118. bufnum_mask = 0x3;
  119. } else {
  120. page_size = 512;
  121. bufnum_mask = 0xf;
  122. if (port_size == 8)
  123. bad_marker = 5;
  124. }
  125. ver = ifc_in32(&gregs->ifc_rev);
  126. if (ver >= FSL_IFC_V2_0_0)
  127. bufnum_mask = (bufnum_mask * 2) + 1;
  128. pages_per_blk =
  129. 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
  130. blk_size = pages_per_blk * page_size;
  131. /* Open Full SRAM mapping for spare are access */
  132. ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
  133. /* Clear Boot events */
  134. ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
  135. /* Program FIR/FCR for Large/Small page */
  136. if (page_size > 512) {
  137. ifc_out32(&ifc->ifc_nand.nand_fir0,
  138. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  139. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  140. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  141. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  142. (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
  143. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  144. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  145. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  146. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  147. } else {
  148. ifc_out32(&ifc->ifc_nand.nand_fir0,
  149. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  150. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  151. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  152. (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
  153. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  154. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  155. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  156. }
  157. /* Program FBCR = 0 for full page read */
  158. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  159. /* Read and copy u-boot on SDRAM from NAND device, In parallel
  160. * check for Bad block if found skip it and read continue to
  161. * next Block
  162. */
  163. while (pos < uboot_size) {
  164. int i = 0;
  165. do {
  166. pg_no = offs / page_size;
  167. bufnum = pg_no & bufnum_mask;
  168. sram_addr = bufnum * page_size * 2;
  169. ifc_out32(&ifc->ifc_nand.row0, pg_no);
  170. ifc_out32(&ifc->ifc_nand.col0, 0);
  171. /* start read */
  172. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  173. IFC_NAND_SEQ_STRT_FIR_STRT);
  174. /* wait for read to complete */
  175. nand_wait(&buf[sram_addr], bufnum, page_size);
  176. /*
  177. * If either of the first two pages are marked bad,
  178. * continue to the next block.
  179. */
  180. if (i++ < 2 &&
  181. bad_block(&buf[sram_addr + page_size + bad_marker],
  182. port_size)) {
  183. puts("skipping\n");
  184. offs = (offs + blk_size) & ~(blk_size - 1);
  185. pos &= ~(blk_size - 1);
  186. break;
  187. }
  188. for (j = 0; j < page_size; j++)
  189. dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
  190. pos += page_size;
  191. offs += page_size;
  192. } while ((offs & (blk_size - 1)) && (pos < uboot_size));
  193. }
  194. return 0;
  195. }
  196. /*
  197. * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
  198. * configured and available since this code loads the main U-Boot image
  199. * from NAND into SDRAM and starts from there.
  200. */
  201. void nand_boot(void)
  202. {
  203. __attribute__((noreturn)) void (*uboot)(void);
  204. /*
  205. * Load U-Boot image from NAND into RAM
  206. */
  207. nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
  208. CONFIG_SYS_NAND_U_BOOT_SIZE,
  209. (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
  210. #ifdef CONFIG_NAND_ENV_DST
  211. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  212. (uchar *)CONFIG_NAND_ENV_DST);
  213. #ifdef CONFIG_ENV_OFFSET_REDUND
  214. nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
  215. (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
  216. #endif
  217. #endif
  218. /*
  219. * Jump to U-Boot image
  220. */
  221. #ifdef CONFIG_SPL_FLUSH_IMAGE
  222. /*
  223. * Clean d-cache and invalidate i-cache, to
  224. * make sure that no stale data is executed.
  225. */
  226. flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
  227. #endif
  228. #ifdef CONFIG_CHAIN_OF_TRUST
  229. /*
  230. * U-Boot header is appended at end of U-boot image, so
  231. * calculate U-boot header address using U-boot header size.
  232. */
  233. #define CONFIG_U_BOOT_HDR_ADDR \
  234. ((CONFIG_SYS_NAND_U_BOOT_START + \
  235. CONFIG_SYS_NAND_U_BOOT_SIZE) - \
  236. CONFIG_U_BOOT_HDR_SIZE)
  237. spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
  238. CONFIG_SYS_NAND_U_BOOT_START);
  239. /*
  240. * In case of failure in validation, spl_validate_uboot would
  241. * not return back in case of Production environment with ITS=1.
  242. * Thus U-Boot will not start.
  243. * In Development environment (ITS=0 and SB_EN=1), the function
  244. * may return back in case of non-fatal failures.
  245. */
  246. #endif
  247. uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
  248. uboot();
  249. }
  250. #ifndef CONFIG_SPL_NAND_INIT
  251. void nand_init(void)
  252. {
  253. }
  254. void nand_deselect(void)
  255. {
  256. }
  257. #endif