fsl_ifc_nand.c 29 KB

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  1. /* Integrated Flash Controller NAND Machine Driver
  2. *
  3. * Copyright (c) 2012 Freescale Semiconductor, Inc
  4. *
  5. * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <nand.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/rawnand.h>
  14. #include <linux/mtd/nand_ecc.h>
  15. #include <asm/io.h>
  16. #include <linux/errno.h>
  17. #include <fsl_ifc.h>
  18. #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  19. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  20. #endif
  21. #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
  22. #define ERR_BYTE 0xFF /* Value returned for read bytes
  23. when read failed */
  24. struct fsl_ifc_ctrl;
  25. /* mtd information per set */
  26. struct fsl_ifc_mtd {
  27. struct nand_chip chip;
  28. struct fsl_ifc_ctrl *ctrl;
  29. struct device *dev;
  30. int bank; /* Chip select bank number */
  31. unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  32. u8 __iomem *vbase; /* Chip select base virtual address */
  33. };
  34. /* overview of the fsl ifc controller */
  35. struct fsl_ifc_ctrl {
  36. struct nand_hw_control controller;
  37. struct fsl_ifc_mtd *chips[MAX_BANKS];
  38. /* device info */
  39. struct fsl_ifc regs;
  40. void __iomem *addr; /* Address of assigned IFC buffer */
  41. unsigned int page; /* Last page written to / read from */
  42. unsigned int read_bytes; /* Number of bytes read during command */
  43. unsigned int column; /* Saved column from SEQIN */
  44. unsigned int index; /* Pointer to next byte to 'read' */
  45. unsigned int status; /* status read from NEESR after last op */
  46. unsigned int oob; /* Non zero if operating on OOB data */
  47. unsigned int eccread; /* Non zero for a full-page ECC read */
  48. };
  49. static struct fsl_ifc_ctrl *ifc_ctrl;
  50. /* 512-byte page with 4-bit ECC, 8-bit */
  51. static struct nand_ecclayout oob_512_8bit_ecc4 = {
  52. .eccbytes = 8,
  53. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  54. .oobfree = { {0, 5}, {6, 2} },
  55. };
  56. /* 512-byte page with 4-bit ECC, 16-bit */
  57. static struct nand_ecclayout oob_512_16bit_ecc4 = {
  58. .eccbytes = 8,
  59. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  60. .oobfree = { {2, 6}, },
  61. };
  62. /* 2048-byte page size with 4-bit ECC */
  63. static struct nand_ecclayout oob_2048_ecc4 = {
  64. .eccbytes = 32,
  65. .eccpos = {
  66. 8, 9, 10, 11, 12, 13, 14, 15,
  67. 16, 17, 18, 19, 20, 21, 22, 23,
  68. 24, 25, 26, 27, 28, 29, 30, 31,
  69. 32, 33, 34, 35, 36, 37, 38, 39,
  70. },
  71. .oobfree = { {2, 6}, {40, 24} },
  72. };
  73. /* 4096-byte page size with 4-bit ECC */
  74. static struct nand_ecclayout oob_4096_ecc4 = {
  75. .eccbytes = 64,
  76. .eccpos = {
  77. 8, 9, 10, 11, 12, 13, 14, 15,
  78. 16, 17, 18, 19, 20, 21, 22, 23,
  79. 24, 25, 26, 27, 28, 29, 30, 31,
  80. 32, 33, 34, 35, 36, 37, 38, 39,
  81. 40, 41, 42, 43, 44, 45, 46, 47,
  82. 48, 49, 50, 51, 52, 53, 54, 55,
  83. 56, 57, 58, 59, 60, 61, 62, 63,
  84. 64, 65, 66, 67, 68, 69, 70, 71,
  85. },
  86. .oobfree = { {2, 6}, {72, 56} },
  87. };
  88. /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
  89. static struct nand_ecclayout oob_4096_ecc8 = {
  90. .eccbytes = 128,
  91. .eccpos = {
  92. 8, 9, 10, 11, 12, 13, 14, 15,
  93. 16, 17, 18, 19, 20, 21, 22, 23,
  94. 24, 25, 26, 27, 28, 29, 30, 31,
  95. 32, 33, 34, 35, 36, 37, 38, 39,
  96. 40, 41, 42, 43, 44, 45, 46, 47,
  97. 48, 49, 50, 51, 52, 53, 54, 55,
  98. 56, 57, 58, 59, 60, 61, 62, 63,
  99. 64, 65, 66, 67, 68, 69, 70, 71,
  100. 72, 73, 74, 75, 76, 77, 78, 79,
  101. 80, 81, 82, 83, 84, 85, 86, 87,
  102. 88, 89, 90, 91, 92, 93, 94, 95,
  103. 96, 97, 98, 99, 100, 101, 102, 103,
  104. 104, 105, 106, 107, 108, 109, 110, 111,
  105. 112, 113, 114, 115, 116, 117, 118, 119,
  106. 120, 121, 122, 123, 124, 125, 126, 127,
  107. 128, 129, 130, 131, 132, 133, 134, 135,
  108. },
  109. .oobfree = { {2, 6}, {136, 82} },
  110. };
  111. /* 8192-byte page size with 4-bit ECC */
  112. static struct nand_ecclayout oob_8192_ecc4 = {
  113. .eccbytes = 128,
  114. .eccpos = {
  115. 8, 9, 10, 11, 12, 13, 14, 15,
  116. 16, 17, 18, 19, 20, 21, 22, 23,
  117. 24, 25, 26, 27, 28, 29, 30, 31,
  118. 32, 33, 34, 35, 36, 37, 38, 39,
  119. 40, 41, 42, 43, 44, 45, 46, 47,
  120. 48, 49, 50, 51, 52, 53, 54, 55,
  121. 56, 57, 58, 59, 60, 61, 62, 63,
  122. 64, 65, 66, 67, 68, 69, 70, 71,
  123. 72, 73, 74, 75, 76, 77, 78, 79,
  124. 80, 81, 82, 83, 84, 85, 86, 87,
  125. 88, 89, 90, 91, 92, 93, 94, 95,
  126. 96, 97, 98, 99, 100, 101, 102, 103,
  127. 104, 105, 106, 107, 108, 109, 110, 111,
  128. 112, 113, 114, 115, 116, 117, 118, 119,
  129. 120, 121, 122, 123, 124, 125, 126, 127,
  130. 128, 129, 130, 131, 132, 133, 134, 135,
  131. },
  132. .oobfree = { {2, 6}, {136, 208} },
  133. };
  134. /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
  135. static struct nand_ecclayout oob_8192_ecc8 = {
  136. .eccbytes = 256,
  137. .eccpos = {
  138. 8, 9, 10, 11, 12, 13, 14, 15,
  139. 16, 17, 18, 19, 20, 21, 22, 23,
  140. 24, 25, 26, 27, 28, 29, 30, 31,
  141. 32, 33, 34, 35, 36, 37, 38, 39,
  142. 40, 41, 42, 43, 44, 45, 46, 47,
  143. 48, 49, 50, 51, 52, 53, 54, 55,
  144. 56, 57, 58, 59, 60, 61, 62, 63,
  145. 64, 65, 66, 67, 68, 69, 70, 71,
  146. 72, 73, 74, 75, 76, 77, 78, 79,
  147. 80, 81, 82, 83, 84, 85, 86, 87,
  148. 88, 89, 90, 91, 92, 93, 94, 95,
  149. 96, 97, 98, 99, 100, 101, 102, 103,
  150. 104, 105, 106, 107, 108, 109, 110, 111,
  151. 112, 113, 114, 115, 116, 117, 118, 119,
  152. 120, 121, 122, 123, 124, 125, 126, 127,
  153. 128, 129, 130, 131, 132, 133, 134, 135,
  154. 136, 137, 138, 139, 140, 141, 142, 143,
  155. 144, 145, 146, 147, 148, 149, 150, 151,
  156. 152, 153, 154, 155, 156, 157, 158, 159,
  157. 160, 161, 162, 163, 164, 165, 166, 167,
  158. 168, 169, 170, 171, 172, 173, 174, 175,
  159. 176, 177, 178, 179, 180, 181, 182, 183,
  160. 184, 185, 186, 187, 188, 189, 190, 191,
  161. 192, 193, 194, 195, 196, 197, 198, 199,
  162. 200, 201, 202, 203, 204, 205, 206, 207,
  163. 208, 209, 210, 211, 212, 213, 214, 215,
  164. 216, 217, 218, 219, 220, 221, 222, 223,
  165. 224, 225, 226, 227, 228, 229, 230, 231,
  166. 232, 233, 234, 235, 236, 237, 238, 239,
  167. 240, 241, 242, 243, 244, 245, 246, 247,
  168. 248, 249, 250, 251, 252, 253, 254, 255,
  169. 256, 257, 258, 259, 260, 261, 262, 263,
  170. },
  171. .oobfree = { {2, 6}, {264, 80} },
  172. };
  173. /*
  174. * Generic flash bbt descriptors
  175. */
  176. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  177. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  178. static struct nand_bbt_descr bbt_main_descr = {
  179. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  180. NAND_BBT_2BIT | NAND_BBT_VERSION,
  181. .offs = 2, /* 0 on 8-bit small page */
  182. .len = 4,
  183. .veroffs = 6,
  184. .maxblocks = 4,
  185. .pattern = bbt_pattern,
  186. };
  187. static struct nand_bbt_descr bbt_mirror_descr = {
  188. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  189. NAND_BBT_2BIT | NAND_BBT_VERSION,
  190. .offs = 2, /* 0 on 8-bit small page */
  191. .len = 4,
  192. .veroffs = 6,
  193. .maxblocks = 4,
  194. .pattern = mirror_pattern,
  195. };
  196. /*
  197. * Set up the IFC hardware block and page address fields, and the ifc nand
  198. * structure addr field to point to the correct IFC buffer in memory
  199. */
  200. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  201. {
  202. struct nand_chip *chip = mtd_to_nand(mtd);
  203. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  204. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  205. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  206. int buf_num;
  207. ctrl->page = page_addr;
  208. /* Program ROW0/COL0 */
  209. ifc_out32(&ifc->ifc_nand.row0, page_addr);
  210. ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
  211. buf_num = page_addr & priv->bufnum_mask;
  212. ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
  213. ctrl->index = column;
  214. /* for OOB data point to the second half of the buffer */
  215. if (oob)
  216. ctrl->index += mtd->writesize;
  217. }
  218. static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  219. unsigned int bufnum)
  220. {
  221. struct nand_chip *chip = mtd_to_nand(mtd);
  222. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  223. u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
  224. u32 __iomem *main = (u32 *)addr;
  225. u8 __iomem *oob = addr + mtd->writesize;
  226. int i;
  227. for (i = 0; i < mtd->writesize / 4; i++) {
  228. if (__raw_readl(&main[i]) != 0xffffffff)
  229. return 0;
  230. }
  231. for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
  232. int pos = chip->ecc.layout->eccpos[i];
  233. if (__raw_readb(&oob[pos]) != 0xff)
  234. return 0;
  235. }
  236. return 1;
  237. }
  238. /* returns nonzero if entire page is blank */
  239. static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  240. u32 *eccstat, unsigned int bufnum)
  241. {
  242. u32 reg = eccstat[bufnum / 4];
  243. int errors;
  244. errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
  245. return errors;
  246. }
  247. /*
  248. * execute IFC NAND command and wait for it to complete
  249. */
  250. static int fsl_ifc_run_command(struct mtd_info *mtd)
  251. {
  252. struct nand_chip *chip = mtd_to_nand(mtd);
  253. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  254. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  255. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  256. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  257. u32 time_start;
  258. u32 eccstat[8] = {0};
  259. int i;
  260. /* set the chip select for NAND Transaction */
  261. ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  262. /* start read/write seq */
  263. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  264. IFC_NAND_SEQ_STRT_FIR_STRT);
  265. /* wait for NAND Machine complete flag or timeout */
  266. time_start = get_timer(0);
  267. while (get_timer(time_start) < timeo) {
  268. ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  269. if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  270. break;
  271. }
  272. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
  273. if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
  274. printf("%s: Flash Time Out Error\n", __func__);
  275. if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
  276. printf("%s: Write Protect Error\n", __func__);
  277. if (ctrl->eccread) {
  278. int errors;
  279. int bufnum = ctrl->page & priv->bufnum_mask;
  280. int sector = bufnum * chip->ecc.steps;
  281. int sector_end = sector + chip->ecc.steps - 1;
  282. for (i = sector / 4; i <= sector_end / 4; i++) {
  283. if (i >= ARRAY_SIZE(eccstat)) {
  284. printf("%s: eccstat too small for %d\n",
  285. __func__, i);
  286. return -EIO;
  287. }
  288. eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  289. }
  290. for (i = sector; i <= sector_end; i++) {
  291. errors = check_read_ecc(mtd, ctrl, eccstat, i);
  292. if (errors == 15) {
  293. /*
  294. * Uncorrectable error.
  295. * OK only if the whole page is blank.
  296. *
  297. * We disable ECCER reporting due to erratum
  298. * IFC-A002770 -- so report it now if we
  299. * see an uncorrectable error in ECCSTAT.
  300. */
  301. if (!is_blank(mtd, ctrl, bufnum))
  302. ctrl->status |=
  303. IFC_NAND_EVTER_STAT_ECCER;
  304. break;
  305. }
  306. mtd->ecc_stats.corrected += errors;
  307. }
  308. ctrl->eccread = 0;
  309. }
  310. /* returns 0 on success otherwise non-zero) */
  311. return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
  312. }
  313. static void fsl_ifc_do_read(struct nand_chip *chip,
  314. int oob,
  315. struct mtd_info *mtd)
  316. {
  317. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  318. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  319. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  320. /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
  321. if (mtd->writesize > 512) {
  322. ifc_out32(&ifc->ifc_nand.nand_fir0,
  323. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  324. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  325. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  326. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  327. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
  328. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  329. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  330. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  331. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  332. } else {
  333. ifc_out32(&ifc->ifc_nand.nand_fir0,
  334. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  335. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  336. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  337. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
  338. if (oob)
  339. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  340. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
  341. else
  342. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  343. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  344. }
  345. }
  346. /* cmdfunc send commands to the IFC NAND Machine */
  347. static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  348. int column, int page_addr)
  349. {
  350. struct nand_chip *chip = mtd_to_nand(mtd);
  351. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  352. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  353. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  354. /* clear the read buffer */
  355. ctrl->read_bytes = 0;
  356. if (command != NAND_CMD_PAGEPROG)
  357. ctrl->index = 0;
  358. switch (command) {
  359. /* READ0 read the entire buffer to use hardware ECC. */
  360. case NAND_CMD_READ0: {
  361. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  362. set_addr(mtd, 0, page_addr, 0);
  363. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  364. ctrl->index += column;
  365. if (chip->ecc.mode == NAND_ECC_HW)
  366. ctrl->eccread = 1;
  367. fsl_ifc_do_read(chip, 0, mtd);
  368. fsl_ifc_run_command(mtd);
  369. return;
  370. }
  371. /* READOOB reads only the OOB because no ECC is performed. */
  372. case NAND_CMD_READOOB:
  373. ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
  374. set_addr(mtd, column, page_addr, 1);
  375. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  376. fsl_ifc_do_read(chip, 1, mtd);
  377. fsl_ifc_run_command(mtd);
  378. return;
  379. /* READID must read all possible bytes while CEB is active */
  380. case NAND_CMD_READID:
  381. case NAND_CMD_PARAM: {
  382. int timing = IFC_FIR_OP_RB;
  383. if (command == NAND_CMD_PARAM)
  384. timing = IFC_FIR_OP_RBCD;
  385. ifc_out32(&ifc->ifc_nand.nand_fir0,
  386. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  387. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  388. (timing << IFC_NAND_FIR0_OP2_SHIFT));
  389. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  390. command << IFC_NAND_FCR0_CMD0_SHIFT);
  391. ifc_out32(&ifc->ifc_nand.row3, column);
  392. /*
  393. * although currently it's 8 bytes for READID, we always read
  394. * the maximum 256 bytes(for PARAM)
  395. */
  396. ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
  397. ctrl->read_bytes = 256;
  398. set_addr(mtd, 0, 0, 0);
  399. fsl_ifc_run_command(mtd);
  400. return;
  401. }
  402. /* ERASE1 stores the block and page address */
  403. case NAND_CMD_ERASE1:
  404. set_addr(mtd, 0, page_addr, 0);
  405. return;
  406. /* ERASE2 uses the block and page address from ERASE1 */
  407. case NAND_CMD_ERASE2:
  408. ifc_out32(&ifc->ifc_nand.nand_fir0,
  409. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  410. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  411. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
  412. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  413. (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  414. (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
  415. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  416. ctrl->read_bytes = 0;
  417. fsl_ifc_run_command(mtd);
  418. return;
  419. /* SEQIN sets up the addr buffer and all registers except the length */
  420. case NAND_CMD_SEQIN: {
  421. u32 nand_fcr0;
  422. ctrl->column = column;
  423. ctrl->oob = 0;
  424. if (mtd->writesize > 512) {
  425. nand_fcr0 =
  426. (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
  427. (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
  428. (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
  429. ifc_out32(&ifc->ifc_nand.nand_fir0,
  430. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  431. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  432. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  433. (IFC_FIR_OP_WBCD <<
  434. IFC_NAND_FIR0_OP3_SHIFT) |
  435. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
  436. ifc_out32(&ifc->ifc_nand.nand_fir1,
  437. (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
  438. (IFC_FIR_OP_RDSTAT <<
  439. IFC_NAND_FIR1_OP6_SHIFT) |
  440. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
  441. } else {
  442. nand_fcr0 = ((NAND_CMD_PAGEPROG <<
  443. IFC_NAND_FCR0_CMD1_SHIFT) |
  444. (NAND_CMD_SEQIN <<
  445. IFC_NAND_FCR0_CMD2_SHIFT) |
  446. (NAND_CMD_STATUS <<
  447. IFC_NAND_FCR0_CMD3_SHIFT));
  448. ifc_out32(&ifc->ifc_nand.nand_fir0,
  449. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  450. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  451. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  452. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  453. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
  454. ifc_out32(&ifc->ifc_nand.nand_fir1,
  455. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
  456. (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
  457. (IFC_FIR_OP_RDSTAT <<
  458. IFC_NAND_FIR1_OP7_SHIFT) |
  459. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
  460. if (column >= mtd->writesize)
  461. nand_fcr0 |=
  462. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
  463. else
  464. nand_fcr0 |=
  465. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
  466. }
  467. if (column >= mtd->writesize) {
  468. /* OOB area --> READOOB */
  469. column -= mtd->writesize;
  470. ctrl->oob = 1;
  471. }
  472. ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
  473. set_addr(mtd, column, page_addr, ctrl->oob);
  474. return;
  475. }
  476. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  477. case NAND_CMD_PAGEPROG:
  478. if (ctrl->oob)
  479. ifc_out32(&ifc->ifc_nand.nand_fbcr,
  480. ctrl->index - ctrl->column);
  481. else
  482. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  483. fsl_ifc_run_command(mtd);
  484. return;
  485. case NAND_CMD_STATUS:
  486. ifc_out32(&ifc->ifc_nand.nand_fir0,
  487. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  488. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
  489. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  490. NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
  491. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  492. set_addr(mtd, 0, 0, 0);
  493. ctrl->read_bytes = 1;
  494. fsl_ifc_run_command(mtd);
  495. /*
  496. * The chip always seems to report that it is
  497. * write-protected, even when it is not.
  498. */
  499. if (chip->options & NAND_BUSWIDTH_16)
  500. ifc_out16(ctrl->addr,
  501. ifc_in16(ctrl->addr) | NAND_STATUS_WP);
  502. else
  503. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  504. return;
  505. case NAND_CMD_RESET:
  506. ifc_out32(&ifc->ifc_nand.nand_fir0,
  507. IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
  508. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  509. NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
  510. fsl_ifc_run_command(mtd);
  511. return;
  512. default:
  513. printf("%s: error, unsupported command 0x%x.\n",
  514. __func__, command);
  515. }
  516. }
  517. /*
  518. * Write buf to the IFC NAND Controller Data Buffer
  519. */
  520. static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  521. {
  522. struct nand_chip *chip = mtd_to_nand(mtd);
  523. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  524. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  525. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  526. if (len <= 0) {
  527. printf("%s of %d bytes", __func__, len);
  528. ctrl->status = 0;
  529. return;
  530. }
  531. if ((unsigned int)len > bufsize - ctrl->index) {
  532. printf("%s beyond end of buffer "
  533. "(%d requested, %u available)\n",
  534. __func__, len, bufsize - ctrl->index);
  535. len = bufsize - ctrl->index;
  536. }
  537. memcpy_toio(ctrl->addr + ctrl->index, buf, len);
  538. ctrl->index += len;
  539. }
  540. /*
  541. * read a byte from either the IFC hardware buffer if it has any data left
  542. * otherwise issue a command to read a single byte.
  543. */
  544. static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
  545. {
  546. struct nand_chip *chip = mtd_to_nand(mtd);
  547. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  548. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  549. unsigned int offset;
  550. /*
  551. * If there are still bytes in the IFC buffer, then use the
  552. * next byte.
  553. */
  554. if (ctrl->index < ctrl->read_bytes) {
  555. offset = ctrl->index++;
  556. return in_8(ctrl->addr + offset);
  557. }
  558. printf("%s beyond end of buffer\n", __func__);
  559. return ERR_BYTE;
  560. }
  561. /*
  562. * Read two bytes from the IFC hardware buffer
  563. * read function for 16-bit buswith
  564. */
  565. static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  566. {
  567. struct nand_chip *chip = mtd_to_nand(mtd);
  568. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  569. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  570. uint16_t data;
  571. /*
  572. * If there are still bytes in the IFC buffer, then use the
  573. * next byte.
  574. */
  575. if (ctrl->index < ctrl->read_bytes) {
  576. data = ifc_in16(ctrl->addr + ctrl->index);
  577. ctrl->index += 2;
  578. return (uint8_t)data;
  579. }
  580. printf("%s beyond end of buffer\n", __func__);
  581. return ERR_BYTE;
  582. }
  583. /*
  584. * Read from the IFC Controller Data Buffer
  585. */
  586. static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  587. {
  588. struct nand_chip *chip = mtd_to_nand(mtd);
  589. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  590. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  591. int avail;
  592. if (len < 0)
  593. return;
  594. avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
  595. memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
  596. ctrl->index += avail;
  597. if (len > avail)
  598. printf("%s beyond end of buffer "
  599. "(%d requested, %d available)\n",
  600. __func__, len, avail);
  601. }
  602. /* This function is called after Program and Erase Operations to
  603. * check for success or failure.
  604. */
  605. static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  606. {
  607. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  608. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  609. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  610. u32 nand_fsr;
  611. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  612. return NAND_STATUS_FAIL;
  613. /* Use READ_STATUS command, but wait for the device to be ready */
  614. ifc_out32(&ifc->ifc_nand.nand_fir0,
  615. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  616. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
  617. ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
  618. IFC_NAND_FCR0_CMD0_SHIFT);
  619. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  620. set_addr(mtd, 0, 0, 0);
  621. ctrl->read_bytes = 1;
  622. fsl_ifc_run_command(mtd);
  623. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  624. return NAND_STATUS_FAIL;
  625. nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
  626. /* Chip sometimes reporting write protect even when it's not */
  627. nand_fsr = nand_fsr | NAND_STATUS_WP;
  628. return nand_fsr;
  629. }
  630. static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  631. uint8_t *buf, int oob_required, int page)
  632. {
  633. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  634. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  635. fsl_ifc_read_buf(mtd, buf, mtd->writesize);
  636. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  637. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  638. mtd->ecc_stats.failed++;
  639. return 0;
  640. }
  641. /* ECC will be calculated automatically, and errors will be detected in
  642. * waitfunc.
  643. */
  644. static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  645. const uint8_t *buf, int oob_required, int page)
  646. {
  647. fsl_ifc_write_buf(mtd, buf, mtd->writesize);
  648. fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  649. return 0;
  650. }
  651. static void fsl_ifc_ctrl_init(void)
  652. {
  653. uint32_t ver = 0;
  654. ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
  655. if (!ifc_ctrl)
  656. return;
  657. ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
  658. ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
  659. if (ver >= FSL_IFC_V2_0_0)
  660. ifc_ctrl->regs.rregs =
  661. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  662. else
  663. ifc_ctrl->regs.rregs =
  664. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  665. /* clear event registers */
  666. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
  667. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
  668. /* Enable error and event for any detected errors */
  669. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
  670. IFC_NAND_EVTER_EN_OPC_EN |
  671. IFC_NAND_EVTER_EN_PGRDCMPL_EN |
  672. IFC_NAND_EVTER_EN_FTOER_EN |
  673. IFC_NAND_EVTER_EN_WPER_EN);
  674. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
  675. }
  676. static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  677. {
  678. }
  679. static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
  680. {
  681. struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
  682. uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
  683. uint32_t ncfgr = 0;
  684. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  685. u32 time_start;
  686. if (ver > FSL_IFC_V1_1_0) {
  687. ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
  688. ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
  689. /* wait for SRAM_INIT bit to be clear or timeout */
  690. time_start = get_timer(0);
  691. while (get_timer(time_start) < timeo) {
  692. ifc_ctrl->status =
  693. ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  694. if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
  695. return 0;
  696. }
  697. printf("fsl-ifc: Failed to Initialise SRAM\n");
  698. return 1;
  699. }
  700. cs = priv->bank;
  701. /* Save CSOR and CSOR_ext */
  702. csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
  703. csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
  704. /* chage PageSize 8K and SpareSize 1K*/
  705. csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
  706. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
  707. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
  708. /* READID */
  709. ifc_out32(&ifc->ifc_nand.nand_fir0,
  710. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  711. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  712. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
  713. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  714. NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
  715. ifc_out32(&ifc->ifc_nand.row3, 0x0);
  716. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
  717. /* Program ROW0/COL0 */
  718. ifc_out32(&ifc->ifc_nand.row0, 0x0);
  719. ifc_out32(&ifc->ifc_nand.col0, 0x0);
  720. /* set the chip select for NAND Transaction */
  721. ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  722. /* start read seq */
  723. ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  724. time_start = get_timer(0);
  725. while (get_timer(time_start) < timeo) {
  726. ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  727. if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  728. break;
  729. }
  730. if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
  731. printf("fsl-ifc: Failed to Initialise SRAM\n");
  732. return 1;
  733. }
  734. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
  735. /* Restore CSOR and CSOR_ext */
  736. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
  737. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
  738. return 0;
  739. }
  740. static int fsl_ifc_chip_init(int devnum, u8 *addr)
  741. {
  742. struct mtd_info *mtd;
  743. struct nand_chip *nand;
  744. struct fsl_ifc_mtd *priv;
  745. struct nand_ecclayout *layout;
  746. struct fsl_ifc_fcm *gregs = NULL;
  747. uint32_t cspr = 0, csor = 0, ver = 0;
  748. int ret = 0;
  749. if (!ifc_ctrl) {
  750. fsl_ifc_ctrl_init();
  751. if (!ifc_ctrl)
  752. return -1;
  753. }
  754. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  755. if (!priv)
  756. return -ENOMEM;
  757. priv->ctrl = ifc_ctrl;
  758. priv->vbase = addr;
  759. gregs = ifc_ctrl->regs.gregs;
  760. /* Find which chip select it is connected to.
  761. */
  762. for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
  763. phys_addr_t phys_addr = virt_to_phys(addr);
  764. cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
  765. csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
  766. if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
  767. (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
  768. break;
  769. }
  770. if (priv->bank >= MAX_BANKS) {
  771. printf("%s: address did not match any "
  772. "chip selects\n", __func__);
  773. kfree(priv);
  774. return -ENODEV;
  775. }
  776. nand = &priv->chip;
  777. mtd = nand_to_mtd(nand);
  778. ifc_ctrl->chips[priv->bank] = priv;
  779. /* fill in nand_chip structure */
  780. /* set up function call table */
  781. nand->write_buf = fsl_ifc_write_buf;
  782. nand->read_buf = fsl_ifc_read_buf;
  783. nand->select_chip = fsl_ifc_select_chip;
  784. nand->cmdfunc = fsl_ifc_cmdfunc;
  785. nand->waitfunc = fsl_ifc_wait;
  786. /* set up nand options */
  787. nand->bbt_td = &bbt_main_descr;
  788. nand->bbt_md = &bbt_mirror_descr;
  789. /* set up nand options */
  790. nand->options = NAND_NO_SUBPAGE_WRITE;
  791. nand->bbt_options = NAND_BBT_USE_FLASH;
  792. if (cspr & CSPR_PORT_SIZE_16) {
  793. nand->read_byte = fsl_ifc_read_byte16;
  794. nand->options |= NAND_BUSWIDTH_16;
  795. } else {
  796. nand->read_byte = fsl_ifc_read_byte;
  797. }
  798. nand->controller = &ifc_ctrl->controller;
  799. nand_set_controller_data(nand, priv);
  800. nand->ecc.read_page = fsl_ifc_read_page;
  801. nand->ecc.write_page = fsl_ifc_write_page;
  802. /* Hardware generates ECC per 512 Bytes */
  803. nand->ecc.size = 512;
  804. nand->ecc.bytes = 8;
  805. switch (csor & CSOR_NAND_PGS_MASK) {
  806. case CSOR_NAND_PGS_512:
  807. if (nand->options & NAND_BUSWIDTH_16) {
  808. layout = &oob_512_16bit_ecc4;
  809. } else {
  810. layout = &oob_512_8bit_ecc4;
  811. /* Avoid conflict with bad block marker */
  812. bbt_main_descr.offs = 0;
  813. bbt_mirror_descr.offs = 0;
  814. }
  815. nand->ecc.strength = 4;
  816. priv->bufnum_mask = 15;
  817. break;
  818. case CSOR_NAND_PGS_2K:
  819. layout = &oob_2048_ecc4;
  820. nand->ecc.strength = 4;
  821. priv->bufnum_mask = 3;
  822. break;
  823. case CSOR_NAND_PGS_4K:
  824. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  825. CSOR_NAND_ECC_MODE_4) {
  826. layout = &oob_4096_ecc4;
  827. nand->ecc.strength = 4;
  828. } else {
  829. layout = &oob_4096_ecc8;
  830. nand->ecc.strength = 8;
  831. nand->ecc.bytes = 16;
  832. }
  833. priv->bufnum_mask = 1;
  834. break;
  835. case CSOR_NAND_PGS_8K:
  836. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  837. CSOR_NAND_ECC_MODE_4) {
  838. layout = &oob_8192_ecc4;
  839. nand->ecc.strength = 4;
  840. } else {
  841. layout = &oob_8192_ecc8;
  842. nand->ecc.strength = 8;
  843. nand->ecc.bytes = 16;
  844. }
  845. priv->bufnum_mask = 0;
  846. break;
  847. default:
  848. printf("ifc nand: bad csor %#x: bad page size\n", csor);
  849. return -ENODEV;
  850. }
  851. /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
  852. if (csor & CSOR_NAND_ECC_DEC_EN) {
  853. nand->ecc.mode = NAND_ECC_HW;
  854. nand->ecc.layout = layout;
  855. } else {
  856. nand->ecc.mode = NAND_ECC_SOFT;
  857. }
  858. ver = ifc_in32(&gregs->ifc_rev);
  859. if (ver >= FSL_IFC_V1_1_0)
  860. ret = fsl_ifc_sram_init(priv, ver);
  861. if (ret)
  862. return ret;
  863. if (ver >= FSL_IFC_V2_0_0)
  864. priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
  865. ret = nand_scan_ident(mtd, 1, NULL);
  866. if (ret)
  867. return ret;
  868. ret = nand_scan_tail(mtd);
  869. if (ret)
  870. return ret;
  871. ret = nand_register(devnum, mtd);
  872. if (ret)
  873. return ret;
  874. return 0;
  875. }
  876. #ifndef CONFIG_SYS_NAND_BASE_LIST
  877. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  878. #endif
  879. static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
  880. CONFIG_SYS_NAND_BASE_LIST;
  881. void board_nand_init(void)
  882. {
  883. int i;
  884. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  885. fsl_ifc_chip_init(i, (u8 *)base_address[i]);
  886. }