fsl_elbc_nand.c 22 KB

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  1. /* Freescale Enhanced Local Bus Controller FCM NAND driver
  2. *
  3. * Copyright (c) 2006-2008 Freescale Semiconductor
  4. *
  5. * Authors: Nick Spence <nick.spence@freescale.com>,
  6. * Scott Wood <scottwood@freescale.com>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <nand.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/rawnand.h>
  15. #include <linux/mtd/nand_ecc.h>
  16. #include <asm/io.h>
  17. #include <linux/errno.h>
  18. #ifdef VERBOSE_DEBUG
  19. #define DEBUG_ELBC
  20. #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  21. #else
  22. #define vdbg(format, arg...) do {} while (0)
  23. #endif
  24. /* Can't use plain old DEBUG because the linux mtd
  25. * headers define it as a macro.
  26. */
  27. #ifdef DEBUG_ELBC
  28. #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  29. #else
  30. #define dbg(format, arg...) do {} while (0)
  31. #endif
  32. #define MAX_BANKS 8
  33. #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  34. #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  35. struct fsl_elbc_ctrl;
  36. /* mtd information per set */
  37. struct fsl_elbc_mtd {
  38. struct nand_chip chip;
  39. struct fsl_elbc_ctrl *ctrl;
  40. struct device *dev;
  41. int bank; /* Chip select bank number */
  42. u8 __iomem *vbase; /* Chip select base virtual address */
  43. int page_size; /* NAND page size (0=512, 1=2048) */
  44. unsigned int fmr; /* FCM Flash Mode Register value */
  45. };
  46. /* overview of the fsl elbc controller */
  47. struct fsl_elbc_ctrl {
  48. struct nand_hw_control controller;
  49. struct fsl_elbc_mtd *chips[MAX_BANKS];
  50. /* device info */
  51. fsl_lbc_t *regs;
  52. u8 __iomem *addr; /* Address of assigned FCM buffer */
  53. unsigned int page; /* Last page written to / read from */
  54. unsigned int read_bytes; /* Number of bytes read during command */
  55. unsigned int column; /* Saved column from SEQIN */
  56. unsigned int index; /* Pointer to next byte to 'read' */
  57. unsigned int status; /* status read from LTESR after last op */
  58. unsigned int mdr; /* UPM/FCM Data Register value */
  59. unsigned int use_mdr; /* Non zero if the MDR is to be set */
  60. unsigned int oob; /* Non zero if operating on OOB data */
  61. };
  62. /* These map to the positions used by the FCM hardware ECC generator */
  63. /* Small Page FLASH with FMR[ECCM] = 0 */
  64. static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  65. .eccbytes = 3,
  66. .eccpos = {6, 7, 8},
  67. .oobfree = { {0, 5}, {9, 7} },
  68. };
  69. /* Small Page FLASH with FMR[ECCM] = 1 */
  70. static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  71. .eccbytes = 3,
  72. .eccpos = {8, 9, 10},
  73. .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  74. };
  75. /* Large Page FLASH with FMR[ECCM] = 0 */
  76. static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  77. .eccbytes = 12,
  78. .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
  79. .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
  80. };
  81. /* Large Page FLASH with FMR[ECCM] = 1 */
  82. static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
  83. .eccbytes = 12,
  84. .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
  85. .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
  86. };
  87. /*
  88. * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
  89. * 1, so we have to adjust bad block pattern. This pattern should be used for
  90. * x8 chips only. So far hardware does not support x16 chips anyway.
  91. */
  92. static u8 scan_ff_pattern[] = { 0xff, };
  93. static struct nand_bbt_descr largepage_memorybased = {
  94. .options = 0,
  95. .offs = 0,
  96. .len = 1,
  97. .pattern = scan_ff_pattern,
  98. };
  99. /*
  100. * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
  101. * interfere with ECC positions, that's why we implement our own descriptors.
  102. * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
  103. */
  104. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  105. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  106. static struct nand_bbt_descr bbt_main_descr = {
  107. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  108. NAND_BBT_2BIT | NAND_BBT_VERSION,
  109. .offs = 11,
  110. .len = 4,
  111. .veroffs = 15,
  112. .maxblocks = 4,
  113. .pattern = bbt_pattern,
  114. };
  115. static struct nand_bbt_descr bbt_mirror_descr = {
  116. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  117. NAND_BBT_2BIT | NAND_BBT_VERSION,
  118. .offs = 11,
  119. .len = 4,
  120. .veroffs = 15,
  121. .maxblocks = 4,
  122. .pattern = mirror_pattern,
  123. };
  124. /*=================================*/
  125. /*
  126. * Set up the FCM hardware block and page address fields, and the fcm
  127. * structure addr field to point to the correct FCM buffer in memory
  128. */
  129. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  130. {
  131. struct nand_chip *chip = mtd_to_nand(mtd);
  132. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  133. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  134. fsl_lbc_t *lbc = ctrl->regs;
  135. int buf_num;
  136. ctrl->page = page_addr;
  137. if (priv->page_size) {
  138. out_be32(&lbc->fbar, page_addr >> 6);
  139. out_be32(&lbc->fpar,
  140. ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
  141. (oob ? FPAR_LP_MS : 0) | column);
  142. buf_num = (page_addr & 1) << 2;
  143. } else {
  144. out_be32(&lbc->fbar, page_addr >> 5);
  145. out_be32(&lbc->fpar,
  146. ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
  147. (oob ? FPAR_SP_MS : 0) | column);
  148. buf_num = page_addr & 7;
  149. }
  150. ctrl->addr = priv->vbase + buf_num * 1024;
  151. ctrl->index = column;
  152. /* for OOB data point to the second half of the buffer */
  153. if (oob)
  154. ctrl->index += priv->page_size ? 2048 : 512;
  155. vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
  156. "index %x, pes %d ps %d\n",
  157. buf_num, ctrl->addr, priv->vbase, ctrl->index,
  158. chip->phys_erase_shift, chip->page_shift);
  159. }
  160. /*
  161. * execute FCM command and wait for it to complete
  162. */
  163. static int fsl_elbc_run_command(struct mtd_info *mtd)
  164. {
  165. struct nand_chip *chip = mtd_to_nand(mtd);
  166. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  167. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  168. fsl_lbc_t *lbc = ctrl->regs;
  169. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  170. u32 time_start;
  171. u32 ltesr;
  172. /* Setup the FMR[OP] to execute without write protection */
  173. out_be32(&lbc->fmr, priv->fmr | 3);
  174. if (ctrl->use_mdr)
  175. out_be32(&lbc->mdr, ctrl->mdr);
  176. vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
  177. in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
  178. vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
  179. "fbcr=%08x bank=%d\n",
  180. in_be32(&lbc->fbar), in_be32(&lbc->fpar),
  181. in_be32(&lbc->fbcr), priv->bank);
  182. /* execute special operation */
  183. out_be32(&lbc->lsor, priv->bank);
  184. /* wait for FCM complete flag or timeout */
  185. time_start = get_timer(0);
  186. ltesr = 0;
  187. while (get_timer(time_start) < timeo) {
  188. ltesr = in_be32(&lbc->ltesr);
  189. if (ltesr & LTESR_CC)
  190. break;
  191. }
  192. ctrl->status = ltesr & LTESR_NAND_MASK;
  193. out_be32(&lbc->ltesr, ctrl->status);
  194. out_be32(&lbc->lteatr, 0);
  195. /* store mdr value in case it was needed */
  196. if (ctrl->use_mdr)
  197. ctrl->mdr = in_be32(&lbc->mdr);
  198. ctrl->use_mdr = 0;
  199. vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
  200. ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
  201. /* returns 0 on success otherwise non-zero) */
  202. return ctrl->status == LTESR_CC ? 0 : -EIO;
  203. }
  204. static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
  205. {
  206. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  207. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  208. fsl_lbc_t *lbc = ctrl->regs;
  209. if (priv->page_size) {
  210. out_be32(&lbc->fir,
  211. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  212. (FIR_OP_CA << FIR_OP1_SHIFT) |
  213. (FIR_OP_PA << FIR_OP2_SHIFT) |
  214. (FIR_OP_CW1 << FIR_OP3_SHIFT) |
  215. (FIR_OP_RBW << FIR_OP4_SHIFT));
  216. out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
  217. (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
  218. } else {
  219. out_be32(&lbc->fir,
  220. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  221. (FIR_OP_CA << FIR_OP1_SHIFT) |
  222. (FIR_OP_PA << FIR_OP2_SHIFT) |
  223. (FIR_OP_RBW << FIR_OP3_SHIFT));
  224. if (oob)
  225. out_be32(&lbc->fcr,
  226. NAND_CMD_READOOB << FCR_CMD0_SHIFT);
  227. else
  228. out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
  229. }
  230. }
  231. /* cmdfunc send commands to the FCM */
  232. static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  233. int column, int page_addr)
  234. {
  235. struct nand_chip *chip = mtd_to_nand(mtd);
  236. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  237. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  238. fsl_lbc_t *lbc = ctrl->regs;
  239. ctrl->use_mdr = 0;
  240. /* clear the read buffer */
  241. ctrl->read_bytes = 0;
  242. if (command != NAND_CMD_PAGEPROG)
  243. ctrl->index = 0;
  244. switch (command) {
  245. /* READ0 and READ1 read the entire buffer to use hardware ECC. */
  246. case NAND_CMD_READ1:
  247. column += 256;
  248. /* fall-through */
  249. case NAND_CMD_READ0:
  250. vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
  251. " 0x%x, column: 0x%x.\n", page_addr, column);
  252. out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
  253. set_addr(mtd, 0, page_addr, 0);
  254. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  255. ctrl->index += column;
  256. fsl_elbc_do_read(chip, 0);
  257. fsl_elbc_run_command(mtd);
  258. return;
  259. /* READOOB reads only the OOB because no ECC is performed. */
  260. case NAND_CMD_READOOB:
  261. vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
  262. " 0x%x, column: 0x%x.\n", page_addr, column);
  263. out_be32(&lbc->fbcr, mtd->oobsize - column);
  264. set_addr(mtd, column, page_addr, 1);
  265. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  266. fsl_elbc_do_read(chip, 1);
  267. fsl_elbc_run_command(mtd);
  268. return;
  269. /* READID must read all 5 possible bytes while CEB is active */
  270. case NAND_CMD_READID:
  271. case NAND_CMD_PARAM:
  272. vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
  273. out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  274. (FIR_OP_UA << FIR_OP1_SHIFT) |
  275. (FIR_OP_RBW << FIR_OP2_SHIFT));
  276. out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
  277. /*
  278. * although currently it's 8 bytes for READID, we always read
  279. * the maximum 256 bytes(for PARAM)
  280. */
  281. out_be32(&lbc->fbcr, 256);
  282. ctrl->read_bytes = 256;
  283. ctrl->use_mdr = 1;
  284. ctrl->mdr = column;
  285. set_addr(mtd, 0, 0, 0);
  286. fsl_elbc_run_command(mtd);
  287. return;
  288. /* ERASE1 stores the block and page address */
  289. case NAND_CMD_ERASE1:
  290. vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
  291. "page_addr: 0x%x.\n", page_addr);
  292. set_addr(mtd, 0, page_addr, 0);
  293. return;
  294. /* ERASE2 uses the block and page address from ERASE1 */
  295. case NAND_CMD_ERASE2:
  296. vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
  297. out_be32(&lbc->fir,
  298. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  299. (FIR_OP_PA << FIR_OP1_SHIFT) |
  300. (FIR_OP_CM1 << FIR_OP2_SHIFT));
  301. out_be32(&lbc->fcr,
  302. (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
  303. (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
  304. out_be32(&lbc->fbcr, 0);
  305. ctrl->read_bytes = 0;
  306. fsl_elbc_run_command(mtd);
  307. return;
  308. /* SEQIN sets up the addr buffer and all registers except the length */
  309. case NAND_CMD_SEQIN: {
  310. u32 fcr;
  311. vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
  312. "page_addr: 0x%x, column: 0x%x.\n",
  313. page_addr, column);
  314. ctrl->column = column;
  315. ctrl->oob = 0;
  316. if (priv->page_size) {
  317. fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
  318. (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
  319. out_be32(&lbc->fir,
  320. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  321. (FIR_OP_CA << FIR_OP1_SHIFT) |
  322. (FIR_OP_PA << FIR_OP2_SHIFT) |
  323. (FIR_OP_WB << FIR_OP3_SHIFT) |
  324. (FIR_OP_CW1 << FIR_OP4_SHIFT));
  325. } else {
  326. fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
  327. (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
  328. out_be32(&lbc->fir,
  329. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  330. (FIR_OP_CM2 << FIR_OP1_SHIFT) |
  331. (FIR_OP_CA << FIR_OP2_SHIFT) |
  332. (FIR_OP_PA << FIR_OP3_SHIFT) |
  333. (FIR_OP_WB << FIR_OP4_SHIFT) |
  334. (FIR_OP_CW1 << FIR_OP5_SHIFT));
  335. if (column >= mtd->writesize) {
  336. /* OOB area --> READOOB */
  337. column -= mtd->writesize;
  338. fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
  339. ctrl->oob = 1;
  340. } else if (column < 256) {
  341. /* First 256 bytes --> READ0 */
  342. fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
  343. } else {
  344. /* Second 256 bytes --> READ1 */
  345. fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
  346. }
  347. }
  348. out_be32(&lbc->fcr, fcr);
  349. set_addr(mtd, column, page_addr, ctrl->oob);
  350. return;
  351. }
  352. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  353. case NAND_CMD_PAGEPROG: {
  354. vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
  355. "writing %d bytes.\n", ctrl->index);
  356. /* if the write did not start at 0 or is not a full page
  357. * then set the exact length, otherwise use a full page
  358. * write so the HW generates the ECC.
  359. */
  360. if (ctrl->oob || ctrl->column != 0 ||
  361. ctrl->index != mtd->writesize + mtd->oobsize)
  362. out_be32(&lbc->fbcr, ctrl->index);
  363. else
  364. out_be32(&lbc->fbcr, 0);
  365. fsl_elbc_run_command(mtd);
  366. return;
  367. }
  368. /* CMD_STATUS must read the status byte while CEB is active */
  369. /* Note - it does not wait for the ready line */
  370. case NAND_CMD_STATUS:
  371. out_be32(&lbc->fir,
  372. (FIR_OP_CM0 << FIR_OP0_SHIFT) |
  373. (FIR_OP_RBW << FIR_OP1_SHIFT));
  374. out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
  375. out_be32(&lbc->fbcr, 1);
  376. set_addr(mtd, 0, 0, 0);
  377. ctrl->read_bytes = 1;
  378. fsl_elbc_run_command(mtd);
  379. /* The chip always seems to report that it is
  380. * write-protected, even when it is not.
  381. */
  382. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  383. return;
  384. /* RESET without waiting for the ready line */
  385. case NAND_CMD_RESET:
  386. dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
  387. out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
  388. out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
  389. fsl_elbc_run_command(mtd);
  390. return;
  391. default:
  392. printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
  393. command);
  394. }
  395. }
  396. static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
  397. {
  398. /* The hardware does not seem to support multiple
  399. * chips per bank.
  400. */
  401. }
  402. /*
  403. * Write buf to the FCM Controller Data Buffer
  404. */
  405. static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  406. {
  407. struct nand_chip *chip = mtd_to_nand(mtd);
  408. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  409. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  410. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  411. if (len <= 0) {
  412. printf("write_buf of %d bytes", len);
  413. ctrl->status = 0;
  414. return;
  415. }
  416. if ((unsigned int)len > bufsize - ctrl->index) {
  417. printf("write_buf beyond end of buffer "
  418. "(%d requested, %u available)\n",
  419. len, bufsize - ctrl->index);
  420. len = bufsize - ctrl->index;
  421. }
  422. memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
  423. /*
  424. * This is workaround for the weird elbc hangs during nand write,
  425. * Scott Wood says: "...perhaps difference in how long it takes a
  426. * write to make it through the localbus compared to a write to IMMR
  427. * is causing problems, and sync isn't helping for some reason."
  428. * Reading back the last byte helps though.
  429. */
  430. in_8(&ctrl->addr[ctrl->index] + len - 1);
  431. ctrl->index += len;
  432. }
  433. /*
  434. * read a byte from either the FCM hardware buffer if it has any data left
  435. * otherwise issue a command to read a single byte.
  436. */
  437. static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
  438. {
  439. struct nand_chip *chip = mtd_to_nand(mtd);
  440. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  441. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  442. /* If there are still bytes in the FCM, then use the next byte. */
  443. if (ctrl->index < ctrl->read_bytes)
  444. return in_8(&ctrl->addr[ctrl->index++]);
  445. printf("read_byte beyond end of buffer\n");
  446. return ERR_BYTE;
  447. }
  448. /*
  449. * Read from the FCM Controller Data Buffer
  450. */
  451. static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  452. {
  453. struct nand_chip *chip = mtd_to_nand(mtd);
  454. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  455. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  456. int avail;
  457. if (len < 0)
  458. return;
  459. avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
  460. memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
  461. ctrl->index += avail;
  462. if (len > avail)
  463. printf("read_buf beyond end of buffer "
  464. "(%d requested, %d available)\n",
  465. len, avail);
  466. }
  467. /* This function is called after Program and Erase Operations to
  468. * check for success or failure.
  469. */
  470. static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  471. {
  472. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  473. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  474. fsl_lbc_t *lbc = ctrl->regs;
  475. if (ctrl->status != LTESR_CC)
  476. return NAND_STATUS_FAIL;
  477. /* Use READ_STATUS command, but wait for the device to be ready */
  478. ctrl->use_mdr = 0;
  479. out_be32(&lbc->fir,
  480. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  481. (FIR_OP_RBW << FIR_OP1_SHIFT));
  482. out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
  483. out_be32(&lbc->fbcr, 1);
  484. set_addr(mtd, 0, 0, 0);
  485. ctrl->read_bytes = 1;
  486. fsl_elbc_run_command(mtd);
  487. if (ctrl->status != LTESR_CC)
  488. return NAND_STATUS_FAIL;
  489. /* The chip always seems to report that it is
  490. * write-protected, even when it is not.
  491. */
  492. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  493. return fsl_elbc_read_byte(mtd);
  494. }
  495. static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  496. uint8_t *buf, int oob_required, int page)
  497. {
  498. fsl_elbc_read_buf(mtd, buf, mtd->writesize);
  499. fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  500. if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
  501. mtd->ecc_stats.failed++;
  502. return 0;
  503. }
  504. /* ECC will be calculated automatically, and errors will be detected in
  505. * waitfunc.
  506. */
  507. static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  508. const uint8_t *buf, int oob_required,
  509. int page)
  510. {
  511. fsl_elbc_write_buf(mtd, buf, mtd->writesize);
  512. fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  513. return 0;
  514. }
  515. static struct fsl_elbc_ctrl *elbc_ctrl;
  516. /* ECC will be calculated automatically, and errors will be detected in
  517. * waitfunc.
  518. */
  519. static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  520. uint32_t offset, uint32_t data_len,
  521. const uint8_t *buf, int oob_required, int page)
  522. {
  523. fsl_elbc_write_buf(mtd, buf, mtd->writesize);
  524. fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  525. return 0;
  526. }
  527. static void fsl_elbc_ctrl_init(void)
  528. {
  529. elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
  530. if (!elbc_ctrl)
  531. return;
  532. elbc_ctrl->regs = LBC_BASE_ADDR;
  533. /* clear event registers */
  534. out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
  535. out_be32(&elbc_ctrl->regs->lteatr, 0);
  536. /* Enable interrupts for any detected events */
  537. out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
  538. elbc_ctrl->read_bytes = 0;
  539. elbc_ctrl->index = 0;
  540. elbc_ctrl->addr = NULL;
  541. }
  542. static int fsl_elbc_chip_init(int devnum, u8 *addr)
  543. {
  544. struct mtd_info *mtd;
  545. struct nand_chip *nand;
  546. struct fsl_elbc_mtd *priv;
  547. uint32_t br = 0, or = 0;
  548. int ret;
  549. if (!elbc_ctrl) {
  550. fsl_elbc_ctrl_init();
  551. if (!elbc_ctrl)
  552. return -1;
  553. }
  554. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  555. if (!priv)
  556. return -ENOMEM;
  557. priv->ctrl = elbc_ctrl;
  558. priv->vbase = addr;
  559. /* Find which chip select it is connected to. It'd be nice
  560. * if we could pass more than one datum to the NAND driver...
  561. */
  562. for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
  563. phys_addr_t phys_addr = virt_to_phys(addr);
  564. br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
  565. or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
  566. if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
  567. (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
  568. break;
  569. }
  570. if (priv->bank >= MAX_BANKS) {
  571. printf("fsl_elbc_nand: address did not match any "
  572. "chip selects\n");
  573. kfree(priv);
  574. return -ENODEV;
  575. }
  576. nand = &priv->chip;
  577. mtd = nand_to_mtd(nand);
  578. elbc_ctrl->chips[priv->bank] = priv;
  579. /* fill in nand_chip structure */
  580. /* set up function call table */
  581. nand->read_byte = fsl_elbc_read_byte;
  582. nand->write_buf = fsl_elbc_write_buf;
  583. nand->read_buf = fsl_elbc_read_buf;
  584. nand->select_chip = fsl_elbc_select_chip;
  585. nand->cmdfunc = fsl_elbc_cmdfunc;
  586. nand->waitfunc = fsl_elbc_wait;
  587. /* set up nand options */
  588. nand->bbt_td = &bbt_main_descr;
  589. nand->bbt_md = &bbt_mirror_descr;
  590. /* set up nand options */
  591. nand->options = NAND_NO_SUBPAGE_WRITE;
  592. nand->bbt_options = NAND_BBT_USE_FLASH;
  593. nand->controller = &elbc_ctrl->controller;
  594. nand_set_controller_data(nand, priv);
  595. nand->ecc.read_page = fsl_elbc_read_page;
  596. nand->ecc.write_page = fsl_elbc_write_page;
  597. nand->ecc.write_subpage = fsl_elbc_write_subpage;
  598. priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
  599. /* If CS Base Register selects full hardware ECC then use it */
  600. if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
  601. nand->ecc.mode = NAND_ECC_HW;
  602. nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
  603. &fsl_elbc_oob_sp_eccm1 :
  604. &fsl_elbc_oob_sp_eccm0;
  605. nand->ecc.size = 512;
  606. nand->ecc.bytes = 3;
  607. nand->ecc.steps = 1;
  608. nand->ecc.strength = 1;
  609. } else {
  610. /* otherwise fall back to software ECC */
  611. #if defined(CONFIG_NAND_ECC_BCH)
  612. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  613. #else
  614. nand->ecc.mode = NAND_ECC_SOFT;
  615. #endif
  616. }
  617. ret = nand_scan_ident(mtd, 1, NULL);
  618. if (ret)
  619. return ret;
  620. /* Large-page-specific setup */
  621. if (mtd->writesize == 2048) {
  622. setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
  623. OR_FCM_PGS);
  624. in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
  625. priv->page_size = 1;
  626. nand->badblock_pattern = &largepage_memorybased;
  627. /*
  628. * Hardware expects small page has ECCM0, large page has
  629. * ECCM1 when booting from NAND, and we follow that even
  630. * when not booting from NAND.
  631. */
  632. priv->fmr |= FMR_ECCM;
  633. /* adjust ecc setup if needed */
  634. if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
  635. nand->ecc.steps = 4;
  636. nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
  637. &fsl_elbc_oob_lp_eccm1 :
  638. &fsl_elbc_oob_lp_eccm0;
  639. }
  640. } else if (mtd->writesize == 512) {
  641. clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
  642. OR_FCM_PGS);
  643. in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
  644. } else {
  645. return -ENODEV;
  646. }
  647. ret = nand_scan_tail(mtd);
  648. if (ret)
  649. return ret;
  650. ret = nand_register(devnum, mtd);
  651. if (ret)
  652. return ret;
  653. return 0;
  654. }
  655. #ifndef CONFIG_SYS_NAND_BASE_LIST
  656. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  657. #endif
  658. static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
  659. CONFIG_SYS_NAND_BASE_LIST;
  660. void board_nand_init(void)
  661. {
  662. int i;
  663. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  664. fsl_elbc_chip_init(i, (u8 *)base_address[i]);
  665. }