picosam9g45.c 8.2 KB

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  1. /*
  2. * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
  3. * (C) Copyright 2015 Inter Act B.V.
  4. *
  5. * Based on:
  6. * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
  7. * (C) Copyright 2007-2008
  8. * Stelian Pop <stelian@popies.net>
  9. * Lead Tech Design <www.leadtechdesign.com>
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clk.h>
  16. #include <asm/arch/at91sam9g45_matrix.h>
  17. #include <asm/arch/at91sam9_smc.h>
  18. #include <asm/arch/at91_common.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/clk.h>
  21. #include <lcd.h>
  22. #include <linux/mtd/rawnand.h>
  23. #include <atmel_lcdc.h>
  24. #include <atmel_mci.h>
  25. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  26. #include <net.h>
  27. #endif
  28. #include <netdev.h>
  29. #include <asm/mach-types.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /* ------------------------------------------------------------------------- */
  32. /*
  33. * Miscelaneous platform dependent initialisations
  34. */
  35. #if defined(CONFIG_SPL_BUILD)
  36. #include <spl.h>
  37. void at91_spl_board_init(void)
  38. {
  39. #ifdef CONFIG_SYS_USE_MMC
  40. at91_mci_hw_init();
  41. #endif
  42. }
  43. #include <asm/arch/atmel_mpddrc.h>
  44. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  45. {
  46. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  47. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  48. ATMEL_MPDDRC_CR_NR_ROW_14 |
  49. ATMEL_MPDDRC_CR_DQMS_SHARED |
  50. ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  51. ddr2->rtr = 0x24b;
  52. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  53. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  54. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  55. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
  56. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  57. 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  58. 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  59. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  60. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  61. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  62. 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  63. 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  64. ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  65. 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  66. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  67. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  68. }
  69. void mem_init(void)
  70. {
  71. struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  72. struct atmel_mpddrc_config ddr2;
  73. unsigned long csa;
  74. ddr2_conf(&ddr2);
  75. at91_system_clk_enable(AT91_PMC_DDR);
  76. /* Chip select 1 is for DDR2/SDRAM */
  77. csa = readl(&mat->ebicsa);
  78. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  79. csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
  80. writel(csa, &mat->ebicsa);
  81. /* DDRAM2 Controller initialize */
  82. ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
  83. ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
  84. }
  85. #endif
  86. #ifdef CONFIG_CMD_USB
  87. static void picosam9g45_usb_hw_init(void)
  88. {
  89. at91_periph_clk_enable(ATMEL_ID_PIODE);
  90. at91_set_gpio_output(AT91_PIN_PD1, 0);
  91. at91_set_gpio_output(AT91_PIN_PD3, 0);
  92. }
  93. #endif
  94. #ifdef CONFIG_MACB
  95. static void picosam9g45_macb_hw_init(void)
  96. {
  97. struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  98. at91_periph_clk_enable(ATMEL_ID_EMAC);
  99. /*
  100. * Disable pull-up on:
  101. * RXDV (PA15) => PHY normal mode (not Test mode)
  102. * ERX0 (PA12) => PHY ADDR0
  103. * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  104. *
  105. * PHY has internal pull-down
  106. */
  107. writel(pin_to_mask(AT91_PIN_PA15) |
  108. pin_to_mask(AT91_PIN_PA12) |
  109. pin_to_mask(AT91_PIN_PA13),
  110. &pioa->pudr);
  111. at91_phy_reset();
  112. /* Re-enable pull-up */
  113. writel(pin_to_mask(AT91_PIN_PA15) |
  114. pin_to_mask(AT91_PIN_PA12) |
  115. pin_to_mask(AT91_PIN_PA13),
  116. &pioa->puer);
  117. /* And the pins. */
  118. at91_macb_hw_init();
  119. }
  120. #endif
  121. #ifdef CONFIG_LCD
  122. vidinfo_t panel_info = {
  123. .vl_col = 480,
  124. .vl_row = 272,
  125. .vl_clk = 9000000,
  126. .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
  127. ATMEL_LCDC_INVFRAME_NORMAL,
  128. .vl_bpix = 3,
  129. .vl_tft = 1,
  130. .vl_hsync_len = 45,
  131. .vl_left_margin = 1,
  132. .vl_right_margin = 1,
  133. .vl_vsync_len = 1,
  134. .vl_upper_margin = 40,
  135. .vl_lower_margin = 1,
  136. .mmio = ATMEL_BASE_LCDC,
  137. };
  138. void lcd_enable(void)
  139. {
  140. at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
  141. }
  142. void lcd_disable(void)
  143. {
  144. at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
  145. }
  146. static void picosam9g45_lcd_hw_init(void)
  147. {
  148. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  149. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  150. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  151. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  152. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  153. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  154. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  155. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  156. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  157. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  158. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  159. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  160. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  161. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  162. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  163. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  164. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  165. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  166. at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  167. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  168. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  169. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  170. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  171. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  172. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  173. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  174. at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  175. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  176. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  177. at91_periph_clk_enable(ATMEL_ID_LCDC);
  178. gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
  179. }
  180. #ifdef CONFIG_LCD_INFO
  181. #include <nand.h>
  182. #include <version.h>
  183. void lcd_show_board_info(void)
  184. {
  185. ulong dram_size;
  186. int i;
  187. char temp[32];
  188. lcd_printf("%s\n", U_BOOT_VERSION);
  189. lcd_printf("(C) 2015 Inter Act B.V.\n");
  190. lcd_printf("support@interact.nl\n");
  191. lcd_printf("%s CPU at %s MHz\n",
  192. ATMEL_CPU_NAME,
  193. strmhz(temp, get_cpu_clk_rate()));
  194. dram_size = 0;
  195. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  196. dram_size += gd->bd->bi_dram[i].size;
  197. lcd_printf(" %ld MB SDRAM\n", dram_size >> 20);
  198. }
  199. #endif /* CONFIG_LCD_INFO */
  200. #endif
  201. #ifdef CONFIG_GENERIC_ATMEL_MCI
  202. int board_mmc_init(bd_t *bis)
  203. {
  204. at91_mci_hw_init();
  205. return atmel_mci_init((void *)ATMEL_BASE_MCI0);
  206. }
  207. #endif
  208. int board_early_init_f(void)
  209. {
  210. at91_seriald_hw_init();
  211. return 0;
  212. }
  213. int board_init(void)
  214. {
  215. gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
  216. /* adress of boot parameters */
  217. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  218. #ifdef CONFIG_CMD_USB
  219. picosam9g45_usb_hw_init();
  220. #endif
  221. #ifdef CONFIG_ATMEL_SPI
  222. at91_spi0_hw_init(1 << 4);
  223. #endif
  224. #ifdef CONFIG_MACB
  225. picosam9g45_macb_hw_init();
  226. #endif
  227. #ifdef CONFIG_LCD
  228. picosam9g45_lcd_hw_init();
  229. #endif
  230. return 0;
  231. }
  232. int dram_init(void)
  233. {
  234. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
  235. + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  236. return 0;
  237. }
  238. int dram_init_banksize(void)
  239. {
  240. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  241. gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
  242. PHYS_SDRAM_1_SIZE);
  243. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  244. gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
  245. PHYS_SDRAM_2_SIZE);
  246. return 0;
  247. }
  248. #ifdef CONFIG_RESET_PHY_R
  249. void reset_phy(void)
  250. {
  251. }
  252. #endif
  253. int board_eth_init(bd_t *bis)
  254. {
  255. int rc = 0;
  256. #ifdef CONFIG_MACB
  257. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  258. #endif
  259. return rc;
  260. }
  261. /* SPI chip select control */
  262. #ifdef CONFIG_ATMEL_SPI
  263. #include <spi.h>
  264. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  265. {
  266. return bus == 0 && cs < 2;
  267. }
  268. void spi_cs_activate(struct spi_slave *slave)
  269. {
  270. switch (slave->cs) {
  271. case 1:
  272. at91_set_gpio_output(AT91_PIN_PB18, 0);
  273. break;
  274. case 0:
  275. default:
  276. at91_set_gpio_output(AT91_PIN_PB3, 0);
  277. break;
  278. }
  279. }
  280. void spi_cs_deactivate(struct spi_slave *slave)
  281. {
  282. switch (slave->cs) {
  283. case 1:
  284. at91_set_gpio_output(AT91_PIN_PB18, 1);
  285. break;
  286. case 0:
  287. default:
  288. at91_set_gpio_output(AT91_PIN_PB3, 1);
  289. break;
  290. }
  291. }
  292. #endif /* CONFIG_ATMEL_SPI */