spl.c 1.7 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0+
  3. */
  4. #include <asm/io.h>
  5. #include <asm/arch/mem.h>
  6. #include <asm/arch/sys_proto.h>
  7. #include <jffs2/load_kernel.h>
  8. #include <linux/mtd/rawnand.h>
  9. #include "igep00x0.h"
  10. /*
  11. * Routine: get_board_mem_timings
  12. * Description: If we use SPL then there is no x-loader nor config header
  13. * so we have to setup the DDR timings ourself on both banks.
  14. */
  15. void get_board_mem_timings(struct board_sdrc_timings *timings)
  16. {
  17. int mfr, id, err = identify_nand_chip(&mfr, &id);
  18. timings->mr = MICRON_V_MR_165;
  19. if (!err) {
  20. switch (mfr) {
  21. case NAND_MFR_HYNIX:
  22. timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  23. timings->ctrla = HYNIX_V_ACTIMA_200;
  24. timings->ctrlb = HYNIX_V_ACTIMB_200;
  25. break;
  26. case NAND_MFR_MICRON:
  27. timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  28. timings->ctrla = MICRON_V_ACTIMA_200;
  29. timings->ctrlb = MICRON_V_ACTIMB_200;
  30. break;
  31. default:
  32. /* Should not happen... */
  33. break;
  34. }
  35. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  36. gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  37. } else {
  38. if (get_cpu_family() == CPU_OMAP34XX) {
  39. timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  40. timings->ctrla = NUMONYX_V_ACTIMA_165;
  41. timings->ctrlb = NUMONYX_V_ACTIMB_165;
  42. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  43. } else {
  44. timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
  45. timings->ctrla = NUMONYX_V_ACTIMA_200;
  46. timings->ctrlb = NUMONYX_V_ACTIMB_200;
  47. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  48. }
  49. gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  50. }
  51. }
  52. #ifdef CONFIG_SPL_OS_BOOT
  53. int spl_start_uboot(void)
  54. {
  55. /* break into full u-boot on 'c' */
  56. if (serial_tstc() && serial_getc() == 'c')
  57. return 1;
  58. return 0;
  59. }
  60. #endif