at91sam9m10g45ek.c 7.8 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian@popies.net>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <debug_uart.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/at91sam9g45_matrix.h>
  13. #include <asm/arch/at91sam9_smc.h>
  14. #include <asm/arch/at91_common.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/clk.h>
  17. #include <lcd.h>
  18. #include <linux/mtd/rawnand.h>
  19. #include <atmel_lcdc.h>
  20. #include <asm/mach-types.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* ------------------------------------------------------------------------- */
  23. /*
  24. * Miscelaneous platform dependent initialisations
  25. */
  26. #ifdef CONFIG_CMD_NAND
  27. void at91sam9m10g45ek_nand_hw_init(void)
  28. {
  29. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  30. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  31. unsigned long csa;
  32. /* Enable CS3 */
  33. csa = readl(&matrix->ebicsa);
  34. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  35. writel(csa, &matrix->ebicsa);
  36. /* Configure SMC CS3 for NAND/SmartMedia */
  37. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  38. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  39. &smc->cs[3].setup);
  40. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  41. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  42. &smc->cs[3].pulse);
  43. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  44. &smc->cs[3].cycle);
  45. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  46. AT91_SMC_MODE_EXNW_DISABLE |
  47. #ifdef CONFIG_SYS_NAND_DBW_16
  48. AT91_SMC_MODE_DBW_16 |
  49. #else /* CONFIG_SYS_NAND_DBW_8 */
  50. AT91_SMC_MODE_DBW_8 |
  51. #endif
  52. AT91_SMC_MODE_TDF_CYCLE(3),
  53. &smc->cs[3].mode);
  54. at91_periph_clk_enable(ATMEL_ID_PIOC);
  55. /* Configure RDY/BSY */
  56. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  57. /* Enable NandFlash */
  58. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  59. }
  60. #endif
  61. #if defined(CONFIG_SPL_BUILD)
  62. #include <spl.h>
  63. #include <nand.h>
  64. void at91_spl_board_init(void)
  65. {
  66. /*
  67. * On the at91sam9m10g45ek board, the chip wm9711 stays in the
  68. * test mode, so it needs do some action to exit test mode.
  69. */
  70. at91_periph_clk_enable(ATMEL_ID_PIODE);
  71. at91_set_gpio_output(AT91_PIN_PD7, 0);
  72. at91_set_gpio_output(AT91_PIN_PD8, 0);
  73. at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
  74. at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
  75. #ifdef CONFIG_SD_BOOT
  76. at91_mci_hw_init();
  77. #elif CONFIG_NAND_BOOT
  78. at91sam9m10g45ek_nand_hw_init();
  79. #endif
  80. }
  81. #include <asm/arch/atmel_mpddrc.h>
  82. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  83. {
  84. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  85. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  86. ATMEL_MPDDRC_CR_NR_ROW_14 |
  87. ATMEL_MPDDRC_CR_DQMS_SHARED |
  88. ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  89. ddr2->rtr = 0x24b;
  90. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  91. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  92. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  93. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
  94. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  95. 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  96. 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  97. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  98. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  99. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  100. 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  101. 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  102. ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  103. 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  104. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  105. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  106. }
  107. void mem_init(void)
  108. {
  109. struct atmel_mpddrc_config ddr2;
  110. ddr2_conf(&ddr2);
  111. at91_system_clk_enable(AT91_PMC_DDR);
  112. /* DDRAM2 Controller initialize */
  113. ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
  114. }
  115. #endif
  116. #ifdef CONFIG_CMD_USB
  117. static void at91sam9m10g45ek_usb_hw_init(void)
  118. {
  119. at91_periph_clk_enable(ATMEL_ID_PIODE);
  120. at91_set_gpio_output(AT91_PIN_PD1, 0);
  121. at91_set_gpio_output(AT91_PIN_PD3, 0);
  122. }
  123. #endif
  124. #ifdef CONFIG_LCD
  125. vidinfo_t panel_info = {
  126. .vl_col = 480,
  127. .vl_row = 272,
  128. .vl_clk = 9000000,
  129. .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
  130. ATMEL_LCDC_INVFRAME_NORMAL,
  131. .vl_bpix = 3,
  132. .vl_tft = 1,
  133. .vl_hsync_len = 45,
  134. .vl_left_margin = 1,
  135. .vl_right_margin = 1,
  136. .vl_vsync_len = 1,
  137. .vl_upper_margin = 40,
  138. .vl_lower_margin = 1,
  139. .mmio = ATMEL_BASE_LCDC,
  140. };
  141. void lcd_enable(void)
  142. {
  143. at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
  144. }
  145. void lcd_disable(void)
  146. {
  147. at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
  148. }
  149. static void at91sam9m10g45ek_lcd_hw_init(void)
  150. {
  151. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  152. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  153. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  154. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  155. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  156. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  157. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  158. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  159. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  160. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  161. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  162. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  163. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  164. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  165. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  166. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  167. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  168. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  169. at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  170. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  171. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  172. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  173. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  174. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  175. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  176. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  177. at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  178. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  179. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  180. at91_periph_clk_enable(ATMEL_ID_LCDC);
  181. gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
  182. }
  183. #ifdef CONFIG_LCD_INFO
  184. #include <nand.h>
  185. #include <version.h>
  186. void lcd_show_board_info(void)
  187. {
  188. ulong dram_size, nand_size;
  189. int i;
  190. char temp[32];
  191. lcd_printf ("%s\n", U_BOOT_VERSION);
  192. lcd_printf ("(C) 2008 ATMEL Corp\n");
  193. lcd_printf ("at91support@atmel.com\n");
  194. lcd_printf ("%s CPU at %s MHz\n",
  195. ATMEL_CPU_NAME,
  196. strmhz(temp, get_cpu_clk_rate()));
  197. dram_size = 0;
  198. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  199. dram_size += gd->bd->bi_dram[i].size;
  200. nand_size = 0;
  201. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  202. nand_size += get_nand_dev_by_index(i)->size;
  203. lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
  204. dram_size >> 20,
  205. nand_size >> 20 );
  206. }
  207. #endif /* CONFIG_LCD_INFO */
  208. #endif
  209. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  210. void board_debug_uart_init(void)
  211. {
  212. at91_seriald_hw_init();
  213. }
  214. #endif
  215. #ifdef CONFIG_BOARD_EARLY_INIT_F
  216. int board_early_init_f(void)
  217. {
  218. #ifdef CONFIG_DEBUG_UART
  219. debug_uart_init();
  220. #endif
  221. return 0;
  222. }
  223. #endif
  224. int board_init(void)
  225. {
  226. /* arch number of AT91SAM9M10G45EK-Board */
  227. #ifdef CONFIG_AT91SAM9M10G45EK
  228. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
  229. #elif defined CONFIG_AT91SAM9G45EKES
  230. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
  231. #endif
  232. /* adress of boot parameters */
  233. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  234. #ifdef CONFIG_CMD_NAND
  235. at91sam9m10g45ek_nand_hw_init();
  236. #endif
  237. #ifdef CONFIG_CMD_USB
  238. at91sam9m10g45ek_usb_hw_init();
  239. #endif
  240. #ifdef CONFIG_LCD
  241. at91sam9m10g45ek_lcd_hw_init();
  242. #endif
  243. return 0;
  244. }
  245. int dram_init(void)
  246. {
  247. gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
  248. CONFIG_SYS_SDRAM_SIZE);
  249. return 0;
  250. }
  251. #ifdef CONFIG_RESET_PHY_R
  252. void reset_phy(void)
  253. {
  254. }
  255. #endif