spl_id_nand.c 1.5 KB

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  1. /*
  2. * (C) Copyright 2011
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Author :
  6. * Tom Rini <trini@ti.com>
  7. *
  8. * Initial Code from:
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Jian Zhang <jzhang@ti.com>
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <jffs2/load_kernel.h>
  16. #include <linux/mtd/rawnand.h>
  17. #include <linux/mtd/omap_gpmc.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/mem.h>
  21. /*
  22. * Many boards will want to know the results of the NAND_CMD_READID command
  23. * in order to decide what to do about DDR initialization. This function
  24. * allows us to do that very early and to pass those results back to the
  25. * board so it can make whatever decisions need to be made.
  26. */
  27. int identify_nand_chip(int *mfr, int *id)
  28. {
  29. int loops = 1000;
  30. /* Make sure that we have setup GPMC for NAND correctly. */
  31. set_gpmc_cs0(MTD_DEV_TYPE_NAND);
  32. sdelay(2000);
  33. /* Issue a RESET and then READID */
  34. writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  35. writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  36. while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  37. != NAND_STATUS_READY) {
  38. sdelay(100);
  39. if (--loops == 0)
  40. return 1;
  41. }
  42. writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
  43. /* Set the address to read to 0x0 */
  44. writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
  45. /* Read off the manufacturer and device id. */
  46. *mfr = readb(&gpmc_cfg->cs[0].nand_dat);
  47. *id = readb(&gpmc_cfg->cs[0].nand_dat);
  48. return 0;
  49. }