davinci_nand.h 2.3 KB

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  1. /*
  2. * NAND Flash Driver
  3. *
  4. * Copyright (C) 2006-2014 Texas Instruments.
  5. *
  6. * Based on Linux DaVinci NAND driver by TI.
  7. */
  8. #ifndef _DAVINCI_NAND_H_
  9. #define _DAVINCI_NAND_H_
  10. #include <linux/mtd/rawnand.h>
  11. #include <asm/arch/hardware.h>
  12. #define NAND_READ_START 0x00
  13. #define NAND_READ_END 0x30
  14. #define NAND_STATUS 0x70
  15. #define MASK_CLE 0x10
  16. #define MASK_ALE 0x08
  17. #ifdef CONFIG_SYS_NAND_MASK_CLE
  18. #undef MASK_CLE
  19. #define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
  20. #endif
  21. #ifdef CONFIG_SYS_NAND_MASK_ALE
  22. #undef MASK_ALE
  23. #define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
  24. #endif
  25. struct davinci_emif_regs {
  26. uint32_t ercsr;
  27. uint32_t awccr;
  28. uint32_t sdbcr;
  29. uint32_t sdrcr;
  30. union {
  31. uint32_t abncr[4];
  32. struct {
  33. uint32_t ab1cr;
  34. uint32_t ab2cr;
  35. uint32_t ab3cr;
  36. uint32_t ab4cr;
  37. };
  38. };
  39. uint32_t sdtimr;
  40. uint32_t ddrsr;
  41. uint32_t ddrphycr;
  42. uint32_t ddrphysr;
  43. uint32_t totar;
  44. uint32_t totactr;
  45. uint32_t ddrphyid_rev;
  46. uint32_t sdsretr;
  47. uint32_t eirr;
  48. uint32_t eimr;
  49. uint32_t eimsr;
  50. uint32_t eimcr;
  51. uint32_t ioctrlr;
  52. uint32_t iostatr;
  53. uint32_t rsvd0;
  54. uint32_t one_nand_cr;
  55. uint32_t nandfcr;
  56. uint32_t nandfsr;
  57. uint32_t rsvd1[2];
  58. uint32_t nandfecc[4];
  59. uint32_t rsvd2[15];
  60. uint32_t nand4biteccload;
  61. uint32_t nand4bitecc[4];
  62. uint32_t nanderradd1;
  63. uint32_t nanderradd2;
  64. uint32_t nanderrval1;
  65. uint32_t nanderrval2;
  66. };
  67. #define davinci_emif_regs \
  68. ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
  69. #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
  70. #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
  71. #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
  72. #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
  73. #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
  74. #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
  75. #define DAVINCI_NANDFCR_CS2NAND (1 << 0)
  76. /* Chip Select setup */
  77. #define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
  78. #define DAVINCI_ABCR_EXT_WAIT (1 << 30)
  79. #define DAVINCI_ABCR_WSETUP(n) (n << 26)
  80. #define DAVINCI_ABCR_WSTROBE(n) (n << 20)
  81. #define DAVINCI_ABCR_WHOLD(n) (n << 17)
  82. #define DAVINCI_ABCR_RSETUP(n) (n << 13)
  83. #define DAVINCI_ABCR_RSTROBE(n) (n << 7)
  84. #define DAVINCI_ABCR_RHOLD(n) (n << 4)
  85. #define DAVINCI_ABCR_TA(n) (n << 2)
  86. #define DAVINCI_ABCR_ASIZE_16BIT 1
  87. #define DAVINCI_ABCR_ASIZE_8BIT 0
  88. void davinci_nand_init(struct nand_chip *nand);
  89. #endif