imx-regs.h 26 KB

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  1. /*
  2. * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. * You should have received a copy of the GNU General Public License along
  13. * with this program; if not, write to the Free Software Foundation, Inc.,
  14. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  15. */
  16. #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  17. #define __ASM_ARCH_MX6_IMX_REGS_H__
  18. #define ARCH_MXC
  19. #define CONFIG_SYS_CACHELINE_SIZE 32
  20. #define ROMCP_ARB_BASE_ADDR 0x00000000
  21. #define ROMCP_ARB_END_ADDR 0x000FFFFF
  22. #ifdef CONFIG_MX6SL
  23. #define GPU_2D_ARB_BASE_ADDR 0x02200000
  24. #define GPU_2D_ARB_END_ADDR 0x02203FFF
  25. #define OPENVG_ARB_BASE_ADDR 0x02204000
  26. #define OPENVG_ARB_END_ADDR 0x02207FFF
  27. #else
  28. #define CAAM_ARB_BASE_ADDR 0x00100000
  29. #define CAAM_ARB_END_ADDR 0x00103FFF
  30. #define APBH_DMA_ARB_BASE_ADDR 0x00110000
  31. #define APBH_DMA_ARB_END_ADDR 0x00117FFF
  32. #define HDMI_ARB_BASE_ADDR 0x00120000
  33. #define HDMI_ARB_END_ADDR 0x00128FFF
  34. #define GPU_3D_ARB_BASE_ADDR 0x00130000
  35. #define GPU_3D_ARB_END_ADDR 0x00133FFF
  36. #define GPU_2D_ARB_BASE_ADDR 0x00134000
  37. #define GPU_2D_ARB_END_ADDR 0x00137FFF
  38. #define DTCP_ARB_BASE_ADDR 0x00138000
  39. #define DTCP_ARB_END_ADDR 0x0013BFFF
  40. #endif /* CONFIG_MX6SL */
  41. #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
  42. #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
  43. #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
  44. /* GPV - PL301 configuration ports */
  45. #ifdef CONFIG_MX6SL
  46. #define GPV2_BASE_ADDR 0x00D00000
  47. #else
  48. #define GPV2_BASE_ADDR 0x00200000
  49. #endif
  50. #define GPV3_BASE_ADDR 0x00300000
  51. #define GPV4_BASE_ADDR 0x00800000
  52. #define IRAM_BASE_ADDR 0x00900000
  53. #define SCU_BASE_ADDR 0x00A00000
  54. #define IC_INTERFACES_BASE_ADDR 0x00A00100
  55. #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
  56. #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
  57. #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
  58. #define GPV0_BASE_ADDR 0x00B00000
  59. #define GPV1_BASE_ADDR 0x00C00000
  60. #define PCIE_ARB_BASE_ADDR 0x01000000
  61. #define PCIE_ARB_END_ADDR 0x01FFFFFF
  62. #define AIPS1_ARB_BASE_ADDR 0x02000000
  63. #define AIPS1_ARB_END_ADDR 0x020FFFFF
  64. #define AIPS2_ARB_BASE_ADDR 0x02100000
  65. #define AIPS2_ARB_END_ADDR 0x021FFFFF
  66. #define SATA_ARB_BASE_ADDR 0x02200000
  67. #define SATA_ARB_END_ADDR 0x02203FFF
  68. #define OPENVG_ARB_BASE_ADDR 0x02204000
  69. #define OPENVG_ARB_END_ADDR 0x02207FFF
  70. #define HSI_ARB_BASE_ADDR 0x02208000
  71. #define HSI_ARB_END_ADDR 0x0220BFFF
  72. #define IPU1_ARB_BASE_ADDR 0x02400000
  73. #define IPU1_ARB_END_ADDR 0x027FFFFF
  74. #define IPU2_ARB_BASE_ADDR 0x02800000
  75. #define IPU2_ARB_END_ADDR 0x02BFFFFF
  76. #define WEIM_ARB_BASE_ADDR 0x08000000
  77. #define WEIM_ARB_END_ADDR 0x0FFFFFFF
  78. #ifdef CONFIG_MX6SL
  79. #define MMDC0_ARB_BASE_ADDR 0x80000000
  80. #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
  81. #define MMDC1_ARB_BASE_ADDR 0xC0000000
  82. #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
  83. #else
  84. #define MMDC0_ARB_BASE_ADDR 0x10000000
  85. #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
  86. #define MMDC1_ARB_BASE_ADDR 0x80000000
  87. #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
  88. #endif
  89. #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
  90. #define IPU_SOC_OFFSET 0x00200000
  91. /* Defines for Blocks connected via AIPS (SkyBlue) */
  92. #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
  93. #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
  94. #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
  95. #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
  96. #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
  97. #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
  98. #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
  99. #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
  100. #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
  101. #ifdef CONFIG_MX6SL
  102. #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  103. #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
  104. #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  105. #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
  106. #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
  107. #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
  108. #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
  109. #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
  110. #else
  111. #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  112. #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
  113. #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  114. #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
  115. #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
  116. #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
  117. #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
  118. #endif
  119. #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
  120. #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
  121. #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
  122. #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
  123. #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
  124. #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
  125. #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
  126. #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
  127. #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
  128. #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
  129. #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
  130. #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
  131. #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
  132. #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
  133. #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
  134. #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
  135. #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
  136. #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
  137. #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
  138. #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
  139. #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
  140. #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
  141. #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
  142. #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
  143. #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
  144. #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
  145. #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
  146. #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
  147. #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
  148. #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
  149. #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
  150. #ifdef CONFIG_MX6SL
  151. #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
  152. #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  153. #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  154. #else
  155. #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
  156. #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  157. #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  158. #endif
  159. #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
  160. #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
  161. #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
  162. #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
  163. #ifdef CONFIG_MX6SL
  164. #define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
  165. #define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
  166. #else
  167. #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
  168. #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
  169. #endif
  170. #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
  171. #ifdef CONFIG_MX6SL
  172. #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
  173. #else
  174. #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
  175. #endif
  176. #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
  177. #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
  178. #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
  179. #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
  180. #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
  181. #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
  182. #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
  183. #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
  184. #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
  185. #ifdef CONFIG_MX6SL
  186. #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  187. #else
  188. #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  189. #endif
  190. #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
  191. #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
  192. #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
  193. #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
  194. #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  195. #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
  196. #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
  197. #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
  198. #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
  199. #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
  200. #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
  201. #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  202. #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
  203. #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
  204. #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
  205. #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
  206. #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
  207. #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
  208. #define CHIP_REV_1_0 0x10
  209. #define IRAM_SIZE 0x00040000
  210. #define FEC_QUIRK_ENET_MAC
  211. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  212. #include <asm/types.h>
  213. extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
  214. /* System Reset Controller (SRC) */
  215. struct src {
  216. u32 scr;
  217. u32 sbmr1;
  218. u32 srsr;
  219. u32 reserved1[2];
  220. u32 sisr;
  221. u32 simr;
  222. u32 sbmr2;
  223. u32 gpr1;
  224. u32 gpr2;
  225. u32 gpr3;
  226. u32 gpr4;
  227. u32 gpr5;
  228. u32 gpr6;
  229. u32 gpr7;
  230. u32 gpr8;
  231. u32 gpr9;
  232. u32 gpr10;
  233. };
  234. /* GPR3 bitfields */
  235. #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
  236. #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
  237. #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
  238. #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
  239. #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
  240. #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
  241. #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
  242. #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
  243. #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
  244. #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
  245. #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
  246. #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
  247. #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
  248. #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
  249. #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
  250. #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
  251. #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
  252. #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
  253. #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
  254. #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
  255. #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
  256. #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
  257. #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
  258. #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
  259. #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
  260. #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
  261. #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
  262. #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
  263. #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
  264. #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
  265. #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
  266. #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
  267. #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
  268. #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
  269. #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
  270. #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
  271. #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
  272. #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
  273. #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
  274. #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
  275. struct iomuxc {
  276. u32 gpr[14];
  277. u32 omux[5];
  278. /* mux and pad registers */
  279. };
  280. #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
  281. #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
  282. #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
  283. #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
  284. #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
  285. #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  286. #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  287. #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  288. #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
  289. #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
  290. #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
  291. #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  292. #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  293. #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  294. #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
  295. #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  296. #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  297. #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  298. #define IOMUXC_GPR2_BITMAP_SPWG 0
  299. #define IOMUXC_GPR2_BITMAP_JEIDA 1
  300. #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
  301. #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  302. #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  303. #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  304. #define IOMUXC_GPR2_DATA_WIDTH_18 0
  305. #define IOMUXC_GPR2_DATA_WIDTH_24 1
  306. #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
  307. #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  308. #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  309. #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  310. #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
  311. #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  312. #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  313. #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  314. #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
  315. #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  316. #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  317. #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  318. #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
  319. #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
  320. #define IOMUXC_GPR2_MODE_DISABLED 0
  321. #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
  322. #define IOMUXC_GPR2_MODE_ENABLED_DI1 2
  323. #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
  324. #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  325. #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  326. #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  327. #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  328. #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
  329. #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  330. #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  331. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  332. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  333. /* ECSPI registers */
  334. struct cspi_regs {
  335. u32 rxdata;
  336. u32 txdata;
  337. u32 ctrl;
  338. u32 cfg;
  339. u32 intr;
  340. u32 dma;
  341. u32 stat;
  342. u32 period;
  343. };
  344. /*
  345. * CSPI register definitions
  346. */
  347. #define MXC_ECSPI
  348. #define MXC_CSPICTRL_EN (1 << 0)
  349. #define MXC_CSPICTRL_MODE (1 << 1)
  350. #define MXC_CSPICTRL_XCH (1 << 2)
  351. #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
  352. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  353. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  354. #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
  355. #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
  356. #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
  357. #define MXC_CSPICTRL_MAXBITS 0xfff
  358. #define MXC_CSPICTRL_TC (1 << 7)
  359. #define MXC_CSPICTRL_RXOVF (1 << 6)
  360. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  361. #define MAX_SPI_BYTES 32
  362. /* Bit position inside CTRL register to be associated with SS */
  363. #define MXC_CSPICTRL_CHAN 18
  364. /* Bit position inside CON register to be associated with SS */
  365. #define MXC_CSPICON_POL 4
  366. #define MXC_CSPICON_PHA 0
  367. #define MXC_CSPICON_SSPOL 12
  368. #ifdef CONFIG_MX6SL
  369. #define MXC_SPI_BASE_ADDRESSES \
  370. ECSPI1_BASE_ADDR, \
  371. ECSPI2_BASE_ADDR, \
  372. ECSPI3_BASE_ADDR, \
  373. ECSPI4_BASE_ADDR
  374. #else
  375. #define MXC_SPI_BASE_ADDRESSES \
  376. ECSPI1_BASE_ADDR, \
  377. ECSPI2_BASE_ADDR, \
  378. ECSPI3_BASE_ADDR, \
  379. ECSPI4_BASE_ADDR, \
  380. ECSPI5_BASE_ADDR
  381. #endif
  382. struct ocotp_regs {
  383. u32 ctrl;
  384. u32 ctrl_set;
  385. u32 ctrl_clr;
  386. u32 ctrl_tog;
  387. u32 timing;
  388. u32 rsvd0[3];
  389. u32 data;
  390. u32 rsvd1[3];
  391. u32 read_ctrl;
  392. u32 rsvd2[3];
  393. u32 read_fuse_data;
  394. u32 rsvd3[3];
  395. u32 sw_sticky;
  396. u32 rsvd4[3];
  397. u32 scs;
  398. u32 scs_set;
  399. u32 scs_clr;
  400. u32 scs_tog;
  401. u32 crc_addr;
  402. u32 rsvd5[3];
  403. u32 crc_value;
  404. u32 rsvd6[3];
  405. u32 version;
  406. u32 rsvd7[0xdb];
  407. struct fuse_bank {
  408. u32 fuse_regs[0x20];
  409. } bank[16];
  410. };
  411. struct fuse_bank0_regs {
  412. u32 lock;
  413. u32 rsvd0[3];
  414. u32 uid_low;
  415. u32 rsvd1[3];
  416. u32 uid_high;
  417. u32 rsvd2[0x17];
  418. };
  419. struct fuse_bank4_regs {
  420. u32 sjc_resp_low;
  421. u32 rsvd0[3];
  422. u32 sjc_resp_high;
  423. u32 rsvd1[3];
  424. u32 mac_addr_low;
  425. u32 rsvd2[3];
  426. u32 mac_addr_high;
  427. u32 rsvd3[0xb];
  428. u32 gp1;
  429. u32 rsvd4[3];
  430. u32 gp2;
  431. u32 rsvd5[3];
  432. };
  433. struct aipstz_regs {
  434. u32 mprot0;
  435. u32 mprot1;
  436. u32 rsvd[0xe];
  437. u32 opacr0;
  438. u32 opacr1;
  439. u32 opacr2;
  440. u32 opacr3;
  441. u32 opacr4;
  442. };
  443. struct anatop_regs {
  444. u32 pll_sys; /* 0x000 */
  445. u32 pll_sys_set; /* 0x004 */
  446. u32 pll_sys_clr; /* 0x008 */
  447. u32 pll_sys_tog; /* 0x00c */
  448. u32 usb1_pll_480_ctrl; /* 0x010 */
  449. u32 usb1_pll_480_ctrl_set; /* 0x014 */
  450. u32 usb1_pll_480_ctrl_clr; /* 0x018 */
  451. u32 usb1_pll_480_ctrl_tog; /* 0x01c */
  452. u32 usb2_pll_480_ctrl; /* 0x020 */
  453. u32 usb2_pll_480_ctrl_set; /* 0x024 */
  454. u32 usb2_pll_480_ctrl_clr; /* 0x028 */
  455. u32 usb2_pll_480_ctrl_tog; /* 0x02c */
  456. u32 pll_528; /* 0x030 */
  457. u32 pll_528_set; /* 0x034 */
  458. u32 pll_528_clr; /* 0x038 */
  459. u32 pll_528_tog; /* 0x03c */
  460. u32 pll_528_ss; /* 0x040 */
  461. u32 rsvd0[3];
  462. u32 pll_528_num; /* 0x050 */
  463. u32 rsvd1[3];
  464. u32 pll_528_denom; /* 0x060 */
  465. u32 rsvd2[3];
  466. u32 pll_audio; /* 0x070 */
  467. u32 pll_audio_set; /* 0x074 */
  468. u32 pll_audio_clr; /* 0x078 */
  469. u32 pll_audio_tog; /* 0x07c */
  470. u32 pll_audio_num; /* 0x080 */
  471. u32 rsvd3[3];
  472. u32 pll_audio_denom; /* 0x090 */
  473. u32 rsvd4[3];
  474. u32 pll_video; /* 0x0a0 */
  475. u32 pll_video_set; /* 0x0a4 */
  476. u32 pll_video_clr; /* 0x0a8 */
  477. u32 pll_video_tog; /* 0x0ac */
  478. u32 pll_video_num; /* 0x0b0 */
  479. u32 rsvd5[3];
  480. u32 pll_video_denom; /* 0x0c0 */
  481. u32 rsvd6[3];
  482. u32 pll_mlb; /* 0x0d0 */
  483. u32 pll_mlb_set; /* 0x0d4 */
  484. u32 pll_mlb_clr; /* 0x0d8 */
  485. u32 pll_mlb_tog; /* 0x0dc */
  486. u32 pll_enet; /* 0x0e0 */
  487. u32 pll_enet_set; /* 0x0e4 */
  488. u32 pll_enet_clr; /* 0x0e8 */
  489. u32 pll_enet_tog; /* 0x0ec */
  490. u32 pfd_480; /* 0x0f0 */
  491. u32 pfd_480_set; /* 0x0f4 */
  492. u32 pfd_480_clr; /* 0x0f8 */
  493. u32 pfd_480_tog; /* 0x0fc */
  494. u32 pfd_528; /* 0x100 */
  495. u32 pfd_528_set; /* 0x104 */
  496. u32 pfd_528_clr; /* 0x108 */
  497. u32 pfd_528_tog; /* 0x10c */
  498. u32 reg_1p1; /* 0x110 */
  499. u32 reg_1p1_set; /* 0x114 */
  500. u32 reg_1p1_clr; /* 0x118 */
  501. u32 reg_1p1_tog; /* 0x11c */
  502. u32 reg_3p0; /* 0x120 */
  503. u32 reg_3p0_set; /* 0x124 */
  504. u32 reg_3p0_clr; /* 0x128 */
  505. u32 reg_3p0_tog; /* 0x12c */
  506. u32 reg_2p5; /* 0x130 */
  507. u32 reg_2p5_set; /* 0x134 */
  508. u32 reg_2p5_clr; /* 0x138 */
  509. u32 reg_2p5_tog; /* 0x13c */
  510. u32 reg_core; /* 0x140 */
  511. u32 reg_core_set; /* 0x144 */
  512. u32 reg_core_clr; /* 0x148 */
  513. u32 reg_core_tog; /* 0x14c */
  514. u32 ana_misc0; /* 0x150 */
  515. u32 ana_misc0_set; /* 0x154 */
  516. u32 ana_misc0_clr; /* 0x158 */
  517. u32 ana_misc0_tog; /* 0x15c */
  518. u32 ana_misc1; /* 0x160 */
  519. u32 ana_misc1_set; /* 0x164 */
  520. u32 ana_misc1_clr; /* 0x168 */
  521. u32 ana_misc1_tog; /* 0x16c */
  522. u32 ana_misc2; /* 0x170 */
  523. u32 ana_misc2_set; /* 0x174 */
  524. u32 ana_misc2_clr; /* 0x178 */
  525. u32 ana_misc2_tog; /* 0x17c */
  526. u32 tempsense0; /* 0x180 */
  527. u32 tempsense0_set; /* 0x184 */
  528. u32 tempsense0_clr; /* 0x188 */
  529. u32 tempsense0_tog; /* 0x18c */
  530. u32 tempsense1; /* 0x190 */
  531. u32 tempsense1_set; /* 0x194 */
  532. u32 tempsense1_clr; /* 0x198 */
  533. u32 tempsense1_tog; /* 0x19c */
  534. u32 usb1_vbus_detect; /* 0x1a0 */
  535. u32 usb1_vbus_detect_set; /* 0x1a4 */
  536. u32 usb1_vbus_detect_clr; /* 0x1a8 */
  537. u32 usb1_vbus_detect_tog; /* 0x1ac */
  538. u32 usb1_chrg_detect; /* 0x1b0 */
  539. u32 usb1_chrg_detect_set; /* 0x1b4 */
  540. u32 usb1_chrg_detect_clr; /* 0x1b8 */
  541. u32 usb1_chrg_detect_tog; /* 0x1bc */
  542. u32 usb1_vbus_det_stat; /* 0x1c0 */
  543. u32 usb1_vbus_det_stat_set; /* 0x1c4 */
  544. u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
  545. u32 usb1_vbus_det_stat_tog; /* 0x1cc */
  546. u32 usb1_chrg_det_stat; /* 0x1d0 */
  547. u32 usb1_chrg_det_stat_set; /* 0x1d4 */
  548. u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
  549. u32 usb1_chrg_det_stat_tog; /* 0x1dc */
  550. u32 usb1_loopback; /* 0x1e0 */
  551. u32 usb1_loopback_set; /* 0x1e4 */
  552. u32 usb1_loopback_clr; /* 0x1e8 */
  553. u32 usb1_loopback_tog; /* 0x1ec */
  554. u32 usb1_misc; /* 0x1f0 */
  555. u32 usb1_misc_set; /* 0x1f4 */
  556. u32 usb1_misc_clr; /* 0x1f8 */
  557. u32 usb1_misc_tog; /* 0x1fc */
  558. u32 usb2_vbus_detect; /* 0x200 */
  559. u32 usb2_vbus_detect_set; /* 0x204 */
  560. u32 usb2_vbus_detect_clr; /* 0x208 */
  561. u32 usb2_vbus_detect_tog; /* 0x20c */
  562. u32 usb2_chrg_detect; /* 0x210 */
  563. u32 usb2_chrg_detect_set; /* 0x214 */
  564. u32 usb2_chrg_detect_clr; /* 0x218 */
  565. u32 usb2_chrg_detect_tog; /* 0x21c */
  566. u32 usb2_vbus_det_stat; /* 0x220 */
  567. u32 usb2_vbus_det_stat_set; /* 0x224 */
  568. u32 usb2_vbus_det_stat_clr; /* 0x228 */
  569. u32 usb2_vbus_det_stat_tog; /* 0x22c */
  570. u32 usb2_chrg_det_stat; /* 0x230 */
  571. u32 usb2_chrg_det_stat_set; /* 0x234 */
  572. u32 usb2_chrg_det_stat_clr; /* 0x238 */
  573. u32 usb2_chrg_det_stat_tog; /* 0x23c */
  574. u32 usb2_loopback; /* 0x240 */
  575. u32 usb2_loopback_set; /* 0x244 */
  576. u32 usb2_loopback_clr; /* 0x248 */
  577. u32 usb2_loopback_tog; /* 0x24c */
  578. u32 usb2_misc; /* 0x250 */
  579. u32 usb2_misc_set; /* 0x254 */
  580. u32 usb2_misc_clr; /* 0x258 */
  581. u32 usb2_misc_tog; /* 0x25c */
  582. u32 digprog; /* 0x260 */
  583. u32 reserved1[7];
  584. u32 digprog_sololite; /* 0x280 */
  585. };
  586. #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
  587. #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
  588. #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
  589. #define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
  590. #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
  591. #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
  592. #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
  593. #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
  594. #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
  595. #define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
  596. #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
  597. #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
  598. #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
  599. #define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
  600. #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
  601. #define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
  602. #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
  603. #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
  604. #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
  605. #define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
  606. #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
  607. #define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
  608. #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
  609. struct iomuxc_base_regs {
  610. u32 gpr[14]; /* 0x000 */
  611. u32 obsrv[5]; /* 0x038 */
  612. u32 swmux_ctl[197]; /* 0x04c */
  613. u32 swpad_ctl[250]; /* 0x360 */
  614. u32 swgrp[26]; /* 0x748 */
  615. u32 daisy[104]; /* 0x7b0..94c */
  616. };
  617. struct wdog_regs {
  618. u16 wcr; /* Control */
  619. u16 wsr; /* Service */
  620. u16 wrsr; /* Reset Status */
  621. u16 wicr; /* Interrupt Control */
  622. u16 wmcr; /* Miscellaneous Control */
  623. };
  624. #endif /* __ASSEMBLER__*/
  625. #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */