imx-regs.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547
  1. /*
  2. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
  23. #define __ASM_ARCH_MX5_IMX_REGS_H__
  24. #define ARCH_MXC
  25. #if defined(CONFIG_MX51)
  26. #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
  27. #define IPU_SOC_BASE_ADDR 0x40000000
  28. #define IPU_SOC_OFFSET 0x1E000000
  29. #define SPBA0_BASE_ADDR 0x70000000
  30. #define AIPS1_BASE_ADDR 0x73F00000
  31. #define AIPS2_BASE_ADDR 0x83F00000
  32. #define CSD0_BASE_ADDR 0x90000000
  33. #define CSD1_BASE_ADDR 0xA0000000
  34. #define NFC_BASE_ADDR_AXI 0xCFFF0000
  35. #define CS1_BASE_ADDR 0xB8000000
  36. #elif defined(CONFIG_MX53)
  37. #define IPU_SOC_BASE_ADDR 0x18000000
  38. #define IPU_SOC_OFFSET 0x06000000
  39. #define SPBA0_BASE_ADDR 0x50000000
  40. #define AIPS1_BASE_ADDR 0x53F00000
  41. #define AIPS2_BASE_ADDR 0x63F00000
  42. #define CSD0_BASE_ADDR 0x70000000
  43. #define CSD1_BASE_ADDR 0xB0000000
  44. #define NFC_BASE_ADDR_AXI 0xF7FF0000
  45. #define IRAM_BASE_ADDR 0xF8000000
  46. #define CS1_BASE_ADDR 0xF4000000
  47. #define SATA_BASE_ADDR 0x10000000
  48. #else
  49. #error "CPU_TYPE not defined"
  50. #endif
  51. #define IRAM_SIZE 0x00020000 /* 128 KB */
  52. /*
  53. * SPBA global module enabled #0
  54. */
  55. #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
  56. #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
  57. #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
  58. #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
  59. #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
  60. #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
  61. #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
  62. #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
  63. #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
  64. #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
  65. #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
  66. #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
  67. /*
  68. * AIPS 1
  69. */
  70. #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
  71. #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
  72. #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
  73. #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
  74. #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
  75. #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
  76. #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
  77. #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
  78. #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
  79. #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
  80. #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
  81. #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
  82. #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
  83. #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
  84. #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
  85. #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
  86. #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
  87. #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
  88. #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
  89. #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
  90. #if defined(CONFIG_MX53)
  91. #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
  92. #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
  93. #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
  94. #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
  95. #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
  96. #endif
  97. /*
  98. * AIPS 2
  99. */
  100. #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
  101. #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
  102. #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
  103. #ifdef CONFIG_MX53
  104. #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
  105. #endif
  106. #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
  107. #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
  108. #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
  109. #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
  110. #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
  111. #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
  112. #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
  113. #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
  114. #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
  115. #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
  116. #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
  117. #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
  118. #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
  119. #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
  120. #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
  121. #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
  122. #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
  123. #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
  124. #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
  125. #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
  126. #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
  127. #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
  128. #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
  129. #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
  130. #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
  131. #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
  132. #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
  133. #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
  134. #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
  135. #if defined(CONFIG_MX53)
  136. #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
  137. #endif
  138. /*
  139. * WEIM CSnGCR1
  140. */
  141. #define CSEN 1
  142. #define SWR (1 << 1)
  143. #define SRD (1 << 2)
  144. #define MUM (1 << 3)
  145. #define WFL (1 << 4)
  146. #define RFL (1 << 5)
  147. #define CRE (1 << 6)
  148. #define CREP (1 << 7)
  149. #define BL(x) (((x) & 0x7) << 8)
  150. #define WC (1 << 11)
  151. #define BCD(x) (((x) & 0x3) << 12)
  152. #define BCS(x) (((x) & 0x3) << 14)
  153. #define DSZ(x) (((x) & 0x7) << 16)
  154. #define SP (1 << 19)
  155. #define CSREC(x) (((x) & 0x7) << 20)
  156. #define AUS (1 << 23)
  157. #define GBC(x) (((x) & 0x7) << 24)
  158. #define WP (1 << 27)
  159. #define PSZ(x) (((x) & 0x0f << 28)
  160. /*
  161. * WEIM CSnGCR2
  162. */
  163. #define ADH(x) (((x) & 0x3))
  164. #define DAPS(x) (((x) & 0x0f << 4)
  165. #define DAE (1 << 8)
  166. #define DAP (1 << 9)
  167. #define MUX16_BYP (1 << 12)
  168. /*
  169. * WEIM CSnRCR1
  170. */
  171. #define RCSN(x) (((x) & 0x7))
  172. #define RCSA(x) (((x) & 0x7) << 4)
  173. #define OEN(x) (((x) & 0x7) << 8)
  174. #define OEA(x) (((x) & 0x7) << 12)
  175. #define RADVN(x) (((x) & 0x7) << 16)
  176. #define RAL (1 << 19)
  177. #define RADVA(x) (((x) & 0x7) << 20)
  178. #define RWSC(x) (((x) & 0x3f) << 24)
  179. /*
  180. * WEIM CSnRCR2
  181. */
  182. #define RBEN(x) (((x) & 0x7))
  183. #define RBE (1 << 3)
  184. #define RBEA(x) (((x) & 0x7) << 4)
  185. #define RL(x) (((x) & 0x3) << 8)
  186. #define PAT(x) (((x) & 0x7) << 12)
  187. #define APR (1 << 15)
  188. /*
  189. * WEIM CSnWCR1
  190. */
  191. #define WCSN(x) (((x) & 0x7))
  192. #define WCSA(x) (((x) & 0x7) << 3)
  193. #define WEN(x) (((x) & 0x7) << 6)
  194. #define WEA(x) (((x) & 0x7) << 9)
  195. #define WBEN(x) (((x) & 0x7) << 12)
  196. #define WBEA(x) (((x) & 0x7) << 15)
  197. #define WADVN(x) (((x) & 0x7) << 18)
  198. #define WADVA(x) (((x) & 0x7) << 21)
  199. #define WWSC(x) (((x) & 0x3f) << 24)
  200. #define WBED1 (1 << 30)
  201. #define WAL (1 << 31)
  202. /*
  203. * WEIM CSnWCR2
  204. */
  205. #define WBED 1
  206. #define CS0_128 0
  207. #define CS0_64M_CS1_64M 1
  208. #define CS0_64M_CS1_32M_CS2_32M 2
  209. #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
  210. /*
  211. * CSPI register definitions
  212. */
  213. #define MXC_ECSPI
  214. #define MXC_CSPICTRL_EN (1 << 0)
  215. #define MXC_CSPICTRL_MODE (1 << 1)
  216. #define MXC_CSPICTRL_XCH (1 << 2)
  217. #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
  218. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  219. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  220. #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
  221. #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
  222. #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
  223. #define MXC_CSPICTRL_MAXBITS 0xfff
  224. #define MXC_CSPICTRL_TC (1 << 7)
  225. #define MXC_CSPICTRL_RXOVF (1 << 6)
  226. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  227. #define MAX_SPI_BYTES 32
  228. /* Bit position inside CTRL register to be associated with SS */
  229. #define MXC_CSPICTRL_CHAN 18
  230. /* Bit position inside CON register to be associated with SS */
  231. #define MXC_CSPICON_POL 4
  232. #define MXC_CSPICON_PHA 0
  233. #define MXC_CSPICON_SSPOL 12
  234. #define MXC_SPI_BASE_ADDRESSES \
  235. CSPI1_BASE_ADDR, \
  236. CSPI2_BASE_ADDR, \
  237. CSPI3_BASE_ADDR,
  238. /*
  239. * Number of GPIO pins per port
  240. */
  241. #define GPIO_NUM_PIN 32
  242. #define IIM_SREV 0x24
  243. #define ROM_SI_REV 0x48
  244. #define NFC_BUF_SIZE 0x1000
  245. /* M4IF */
  246. #define M4IF_FBPM0 0x40
  247. #define M4IF_FIDBP 0x48
  248. #define M4IF_GENP_WEIM_MM_MASK 0x00000001
  249. #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
  250. /* Assuming 24MHz input clock with doubler ON */
  251. /* MFI PDF */
  252. #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
  253. #define DP_MFD_864 (180 - 1) /* PL Dither mode */
  254. #define DP_MFN_864 180
  255. #define DP_MFN_800_DIT 60 /* PL Dither mode */
  256. #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
  257. #define DP_MFD_850 (48 - 1)
  258. #define DP_MFN_850 41
  259. #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
  260. #define DP_MFD_800 (3 - 1)
  261. #define DP_MFN_800 1
  262. #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
  263. #define DP_MFD_700 (24 - 1)
  264. #define DP_MFN_700 7
  265. #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
  266. #define DP_MFD_665 (96 - 1)
  267. #define DP_MFN_665 89
  268. #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
  269. #define DP_MFD_532 (24 - 1)
  270. #define DP_MFN_532 13
  271. #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
  272. #define DP_MFD_400 (3 - 1)
  273. #define DP_MFN_400 1
  274. #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
  275. #define DP_MFD_455 (48 - 1)
  276. #define DP_MFN_455 23
  277. #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
  278. #define DP_MFD_216 (4 - 1)
  279. #define DP_MFN_216 3
  280. #define CHIP_REV_1_0 0x10
  281. #define CHIP_REV_1_1 0x11
  282. #define CHIP_REV_2_0 0x20
  283. #define CHIP_REV_2_5 0x25
  284. #define CHIP_REV_3_0 0x30
  285. #define BOARD_REV_1_0 0x0
  286. #define BOARD_REV_2_0 0x1
  287. #define BOARD_VER_OFFSET 0x8
  288. #define IMX_IIM_BASE (IIM_BASE_ADDR)
  289. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  290. #include <asm/types.h>
  291. #define __REG(x) (*((volatile u32 *)(x)))
  292. #define __REG16(x) (*((volatile u16 *)(x)))
  293. #define __REG8(x) (*((volatile u8 *)(x)))
  294. struct clkctl {
  295. u32 ccr;
  296. u32 ccdr;
  297. u32 csr;
  298. u32 ccsr;
  299. u32 cacrr;
  300. u32 cbcdr;
  301. u32 cbcmr;
  302. u32 cscmr1;
  303. u32 cscmr2;
  304. u32 cscdr1;
  305. u32 cs1cdr;
  306. u32 cs2cdr;
  307. u32 cdcdr;
  308. u32 chsccdr;
  309. u32 cscdr2;
  310. u32 cscdr3;
  311. u32 cscdr4;
  312. u32 cwdr;
  313. u32 cdhipr;
  314. u32 cdcr;
  315. u32 ctor;
  316. u32 clpcr;
  317. u32 cisr;
  318. u32 cimr;
  319. u32 ccosr;
  320. u32 cgpr;
  321. u32 ccgr0;
  322. u32 ccgr1;
  323. u32 ccgr2;
  324. u32 ccgr3;
  325. u32 ccgr4;
  326. u32 ccgr5;
  327. u32 ccgr6;
  328. #if defined(CONFIG_MX53)
  329. u32 ccgr7;
  330. #endif
  331. u32 cmeor;
  332. };
  333. /* DPLL registers */
  334. struct dpll {
  335. u32 dp_ctl;
  336. u32 dp_config;
  337. u32 dp_op;
  338. u32 dp_mfd;
  339. u32 dp_mfn;
  340. u32 dp_mfn_minus;
  341. u32 dp_mfn_plus;
  342. u32 dp_hfs_op;
  343. u32 dp_hfs_mfd;
  344. u32 dp_hfs_mfn;
  345. u32 dp_mfn_togc;
  346. u32 dp_destat;
  347. };
  348. /* WEIM registers */
  349. struct weim {
  350. u32 cs0gcr1;
  351. u32 cs0gcr2;
  352. u32 cs0rcr1;
  353. u32 cs0rcr2;
  354. u32 cs0wcr1;
  355. u32 cs0wcr2;
  356. u32 cs1gcr1;
  357. u32 cs1gcr2;
  358. u32 cs1rcr1;
  359. u32 cs1rcr2;
  360. u32 cs1wcr1;
  361. u32 cs1wcr2;
  362. u32 cs2gcr1;
  363. u32 cs2gcr2;
  364. u32 cs2rcr1;
  365. u32 cs2rcr2;
  366. u32 cs2wcr1;
  367. u32 cs2wcr2;
  368. u32 cs3gcr1;
  369. u32 cs3gcr2;
  370. u32 cs3rcr1;
  371. u32 cs3rcr2;
  372. u32 cs3wcr1;
  373. u32 cs3wcr2;
  374. u32 cs4gcr1;
  375. u32 cs4gcr2;
  376. u32 cs4rcr1;
  377. u32 cs4rcr2;
  378. u32 cs4wcr1;
  379. u32 cs4wcr2;
  380. u32 cs5gcr1;
  381. u32 cs5gcr2;
  382. u32 cs5rcr1;
  383. u32 cs5rcr2;
  384. u32 cs5wcr1;
  385. u32 cs5wcr2;
  386. u32 wcr;
  387. u32 wiar;
  388. u32 ear;
  389. };
  390. #if defined(CONFIG_MX51)
  391. struct iomuxc {
  392. u32 gpr0;
  393. u32 gpr1;
  394. u32 omux0;
  395. u32 omux1;
  396. u32 omux2;
  397. u32 omux3;
  398. u32 omux4;
  399. };
  400. #elif defined(CONFIG_MX53)
  401. struct iomuxc {
  402. u32 gpr0;
  403. u32 gpr1;
  404. u32 gpr2;
  405. u32 omux0;
  406. u32 omux1;
  407. u32 omux2;
  408. u32 omux3;
  409. u32 omux4;
  410. };
  411. #endif
  412. /* System Reset Controller (SRC) */
  413. struct src {
  414. u32 scr;
  415. u32 sbmr;
  416. u32 srsr;
  417. u32 reserved1[2];
  418. u32 sisr;
  419. u32 simr;
  420. };
  421. struct srtc_regs {
  422. u32 lpscmr; /* 0x00 */
  423. u32 lpsclr; /* 0x04 */
  424. u32 lpsar; /* 0x08 */
  425. u32 lpsmcr; /* 0x0c */
  426. u32 lpcr; /* 0x10 */
  427. u32 lpsr; /* 0x14 */
  428. u32 lppdr; /* 0x18 */
  429. u32 lpgr; /* 0x1c */
  430. u32 hpcmr; /* 0x20 */
  431. u32 hpclr; /* 0x24 */
  432. u32 hpamr; /* 0x28 */
  433. u32 hpalr; /* 0x2c */
  434. u32 hpcr; /* 0x30 */
  435. u32 hpisr; /* 0x34 */
  436. u32 hpienr; /* 0x38 */
  437. };
  438. /* CSPI registers */
  439. struct cspi_regs {
  440. u32 rxdata;
  441. u32 txdata;
  442. u32 ctrl;
  443. u32 cfg;
  444. u32 intr;
  445. u32 dma;
  446. u32 stat;
  447. u32 period;
  448. };
  449. struct iim_regs {
  450. u32 stat;
  451. u32 statm;
  452. u32 err;
  453. u32 emask;
  454. u32 fctl;
  455. u32 ua;
  456. u32 la;
  457. u32 sdat;
  458. u32 prev;
  459. u32 srev;
  460. u32 prg_p;
  461. u32 scs0;
  462. u32 scs1;
  463. u32 scs2;
  464. u32 scs3;
  465. u32 res0[0x1f1];
  466. struct fuse_bank {
  467. u32 fuse_regs[0x20];
  468. u32 fuse_rsvd[0xe0];
  469. #if defined(CONFIG_MX51)
  470. } bank[4];
  471. #elif defined(CONFIG_MX53)
  472. } bank[5];
  473. #endif
  474. };
  475. struct fuse_bank0_regs {
  476. u32 fuse0_7[8];
  477. u32 uid[8];
  478. u32 fuse16_23[8];
  479. #if defined(CONFIG_MX51)
  480. u32 imei[8];
  481. #elif defined(CONFIG_MX53)
  482. u32 gp[8];
  483. #endif
  484. };
  485. struct fuse_bank1_regs {
  486. u32 fuse0_8[9];
  487. u32 mac_addr[6];
  488. u32 fuse15_31[0x11];
  489. };
  490. #if defined(CONFIG_MX53)
  491. struct fuse_bank4_regs {
  492. u32 fuse0_4[5];
  493. u32 gp[3];
  494. u32 fuse8_31[0x18];
  495. };
  496. #endif
  497. #endif /* __ASSEMBLER__*/
  498. #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */