px30.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <asm/armv8/mmu.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/grf_px30.h>
  12. #include <asm/arch-rockchip/hardware.h>
  13. #include <asm/arch-rockchip/uart.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/cru_px30.h>
  16. #include <dt-bindings/clock/px30-cru.h>
  17. static struct mm_region px30_mem_map[] = {
  18. {
  19. .virt = 0x0UL,
  20. .phys = 0x0UL,
  21. .size = 0xff000000UL,
  22. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  23. PTE_BLOCK_INNER_SHARE
  24. }, {
  25. .virt = 0xff000000UL,
  26. .phys = 0xff000000UL,
  27. .size = 0x01000000UL,
  28. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29. PTE_BLOCK_NON_SHARE |
  30. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31. }, {
  32. /* List terminator */
  33. 0,
  34. }
  35. };
  36. struct mm_region *mem_map = px30_mem_map;
  37. #define PMU_PWRDN_CON 0xff000018
  38. #define PMUGRF_BASE 0xff010000
  39. #define GRF_BASE 0xff140000
  40. #define CRU_BASE 0xff2b0000
  41. #define VIDEO_PHY_BASE 0xff2e0000
  42. #define SERVICE_CORE_ADDR 0xff508000
  43. #define DDR_FW_BASE 0xff534000
  44. #define FW_DDR_CON 0x40
  45. #define QOS_PRIORITY 0x08
  46. #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
  47. /* GRF_GPIO1BH_IOMUX */
  48. enum {
  49. GPIO1B7_SHIFT = 12,
  50. GPIO1B7_MASK = 0xf << GPIO1B7_SHIFT,
  51. GPIO1B7_GPIO = 0,
  52. GPIO1B7_FLASH_RDN,
  53. GPIO1B7_UART3_RXM1,
  54. GPIO1B7_SPI0_CLK,
  55. GPIO1B6_SHIFT = 8,
  56. GPIO1B6_MASK = 0xf << GPIO1B6_SHIFT,
  57. GPIO1B6_GPIO = 0,
  58. GPIO1B6_FLASH_CS1,
  59. GPIO1B6_UART3_TXM1,
  60. GPIO1B6_SPI0_CSN,
  61. };
  62. /* GRF_GPIO1CL_IOMUX */
  63. enum {
  64. GPIO1C1_SHIFT = 4,
  65. GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT,
  66. GPIO1C1_GPIO = 0,
  67. GPIO1C1_UART1_TX,
  68. GPIO1C0_SHIFT = 0,
  69. GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT,
  70. GPIO1C0_GPIO = 0,
  71. GPIO1C0_UART1_RX,
  72. };
  73. /* GRF_GPIO1DL_IOMUX */
  74. enum {
  75. GPIO1D3_SHIFT = 12,
  76. GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT,
  77. GPIO1D3_GPIO = 0,
  78. GPIO1D3_SDMMC_D1,
  79. GPIO1D3_UART2_RXM0,
  80. GPIO1D2_SHIFT = 8,
  81. GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT,
  82. GPIO1D2_GPIO = 0,
  83. GPIO1D2_SDMMC_D0,
  84. GPIO1D2_UART2_TXM0,
  85. };
  86. /* GRF_GPIO1DH_IOMUX */
  87. enum {
  88. GPIO1D7_SHIFT = 12,
  89. GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT,
  90. GPIO1D7_GPIO = 0,
  91. GPIO1D7_SDMMC_CMD,
  92. GPIO1D6_SHIFT = 8,
  93. GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT,
  94. GPIO1D6_GPIO = 0,
  95. GPIO1D6_SDMMC_CLK,
  96. GPIO1D5_SHIFT = 4,
  97. GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT,
  98. GPIO1D5_GPIO = 0,
  99. GPIO1D5_SDMMC_D3,
  100. GPIO1D4_SHIFT = 0,
  101. GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT,
  102. GPIO1D4_GPIO = 0,
  103. GPIO1D4_SDMMC_D2,
  104. };
  105. /* GRF_GPIO2BH_IOMUX */
  106. enum {
  107. GPIO2B6_SHIFT = 8,
  108. GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT,
  109. GPIO2B6_GPIO = 0,
  110. GPIO2B6_CIF_D1M0,
  111. GPIO2B6_UART2_RXM1,
  112. GPIO2B4_SHIFT = 0,
  113. GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT,
  114. GPIO2B4_GPIO = 0,
  115. GPIO2B4_CIF_D0M0,
  116. GPIO2B4_UART2_TXM1,
  117. };
  118. /* GRF_GPIO3AL_IOMUX */
  119. enum {
  120. GPIO3A2_SHIFT = 8,
  121. GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT,
  122. GPIO3A2_GPIO = 0,
  123. GPIO3A2_UART5_TX = 4,
  124. GPIO3A1_SHIFT = 4,
  125. GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT,
  126. GPIO3A1_GPIO = 0,
  127. GPIO3A1_UART5_RX = 4,
  128. };
  129. /* PMUGRF_GPIO0CL_IOMUX */
  130. enum {
  131. GPIO0C1_SHIFT = 2,
  132. GPIO0C1_MASK = 0x3 << GPIO0C1_SHIFT,
  133. GPIO0C1_GPIO = 0,
  134. GPIO0C1_PWM_3,
  135. GPIO0C1_UART3_RXM0,
  136. GPIO0C1_PMU_DEBUG4,
  137. GPIO0C0_SHIFT = 0,
  138. GPIO0C0_MASK = 0x3 << GPIO0C0_SHIFT,
  139. GPIO0C0_GPIO = 0,
  140. GPIO0C0_PWM_1,
  141. GPIO0C0_UART3_TXM0,
  142. GPIO0C0_PMU_DEBUG3,
  143. };
  144. int arch_cpu_init(void)
  145. {
  146. static struct px30_grf * const grf = (void *)GRF_BASE;
  147. u32 __maybe_unused val;
  148. #ifdef CONFIG_SPL_BUILD
  149. /* We do some SoC one time setting here. */
  150. /* Disable the ddr secure region setting to make it non-secure */
  151. writel(0x0, DDR_FW_BASE + FW_DDR_CON);
  152. /* Set cpu qos priority */
  153. writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
  154. #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
  155. (CONFIG_DEBUG_UART_BASE != 0xff160000) || \
  156. (CONFIG_DEBUG_UART_CHANNEL != 0)
  157. /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
  158. rk_clrsetreg(&grf->gpio1dl_iomux,
  159. GPIO1D3_MASK | GPIO1D2_MASK,
  160. GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
  161. GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
  162. rk_clrsetreg(&grf->gpio1dh_iomux,
  163. GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
  164. GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
  165. GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
  166. GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
  167. GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
  168. #endif
  169. #endif
  170. /* Enable PD_VO (default disable at reset) */
  171. rk_clrreg(PMU_PWRDN_CON, 1 << 13);
  172. /* Disable video phy bandgap by default */
  173. writel(0x82, VIDEO_PHY_BASE + 0x0000);
  174. writel(0x05, VIDEO_PHY_BASE + 0x03ac);
  175. /* Clear the force_jtag */
  176. rk_clrreg(&grf->cpu_con[1], 1 << 7);
  177. return 0;
  178. }
  179. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  180. void board_debug_uart_init(void)
  181. {
  182. #if defined(CONFIG_DEBUG_UART_BASE) && \
  183. (CONFIG_DEBUG_UART_BASE == 0xff168000) && \
  184. (CONFIG_DEBUG_UART_CHANNEL != 1)
  185. static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
  186. #endif
  187. static struct px30_grf * const grf = (void *)GRF_BASE;
  188. static struct px30_cru * const cru = (void *)CRU_BASE;
  189. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
  190. /* uart_sel_clk default select 24MHz */
  191. rk_clrsetreg(&cru->clksel_con[34],
  192. UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
  193. UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
  194. rk_clrsetreg(&cru->clksel_con[35],
  195. UART1_CLK_SEL_MASK,
  196. UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
  197. rk_clrsetreg(&grf->gpio1cl_iomux,
  198. GPIO1C1_MASK | GPIO1C0_MASK,
  199. GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
  200. GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
  201. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
  202. /* GRF_IOFUNC_CON0 */
  203. enum {
  204. CON_IOMUX_UART3SEL_SHIFT = 9,
  205. CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
  206. CON_IOMUX_UART3SEL_M0 = 0,
  207. CON_IOMUX_UART3SEL_M1,
  208. };
  209. /* uart_sel_clk default select 24MHz */
  210. rk_clrsetreg(&cru->clksel_con[40],
  211. UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
  212. UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
  213. rk_clrsetreg(&cru->clksel_con[41],
  214. UART3_CLK_SEL_MASK,
  215. UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
  216. #if (CONFIG_DEBUG_UART_CHANNEL == 1)
  217. rk_clrsetreg(&grf->iofunc_con0,
  218. CON_IOMUX_UART3SEL_MASK,
  219. CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
  220. rk_clrsetreg(&grf->gpio1bh_iomux,
  221. GPIO1B7_MASK | GPIO1B6_MASK,
  222. GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
  223. GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
  224. #else
  225. rk_clrsetreg(&grf->iofunc_con0,
  226. CON_IOMUX_UART3SEL_MASK,
  227. CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
  228. rk_clrsetreg(&pmugrf->gpio0cl_iomux,
  229. GPIO0C1_MASK | GPIO0C0_MASK,
  230. GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
  231. GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
  232. #endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
  233. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
  234. /* uart_sel_clk default select 24MHz */
  235. rk_clrsetreg(&cru->clksel_con[46],
  236. UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
  237. UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
  238. rk_clrsetreg(&cru->clksel_con[47],
  239. UART5_CLK_SEL_MASK,
  240. UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
  241. rk_clrsetreg(&grf->gpio3al_iomux,
  242. GPIO3A2_MASK | GPIO3A1_MASK,
  243. GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
  244. GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
  245. #else
  246. /* GRF_IOFUNC_CON0 */
  247. enum {
  248. CON_IOMUX_UART2SEL_SHIFT = 10,
  249. CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
  250. CON_IOMUX_UART2SEL_M0 = 0,
  251. CON_IOMUX_UART2SEL_M1,
  252. CON_IOMUX_UART2SEL_USBPHY,
  253. };
  254. /* uart_sel_clk default select 24MHz */
  255. rk_clrsetreg(&cru->clksel_con[37],
  256. UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
  257. UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
  258. rk_clrsetreg(&cru->clksel_con[38],
  259. UART2_CLK_SEL_MASK,
  260. UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
  261. #if (CONFIG_DEBUG_UART_CHANNEL == 1)
  262. /* Enable early UART2 */
  263. rk_clrsetreg(&grf->iofunc_con0,
  264. CON_IOMUX_UART2SEL_MASK,
  265. CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
  266. rk_clrsetreg(&grf->gpio2bh_iomux,
  267. GPIO2B6_MASK | GPIO2B4_MASK,
  268. GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
  269. GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
  270. #else
  271. rk_clrsetreg(&grf->iofunc_con0,
  272. CON_IOMUX_UART2SEL_MASK,
  273. CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
  274. rk_clrsetreg(&grf->gpio1dl_iomux,
  275. GPIO1D3_MASK | GPIO1D2_MASK,
  276. GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
  277. GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
  278. #endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
  279. #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
  280. }
  281. #endif /* CONFIG_DEBUG_UART_BOARD_INIT */