emif4.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Author :
  4. * Vaibhav Hiremath <hvaibhav@ti.com>
  5. *
  6. * Based on mem.c and sdrc.c
  7. *
  8. * Copyright (C) 2010
  9. * Texas Instruments Incorporated - http://www.ti.com/
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/mem.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/emif4.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. extern omap3_sysinfo sysinfo;
  19. static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
  20. /*
  21. * is_mem_sdr -
  22. * - Return 1 if mem type in use is SDR
  23. */
  24. u32 is_mem_sdr(void)
  25. {
  26. return 0;
  27. }
  28. /*
  29. * get_sdr_cs_size -
  30. * - Get size of chip select 0/1
  31. */
  32. u32 get_sdr_cs_size(u32 cs)
  33. {
  34. u32 size = 0;
  35. /* TODO: Calculate the size based on EMIF4 configuration */
  36. if (cs == CS0)
  37. size = CONFIG_SYS_CS0_SIZE;
  38. return size;
  39. }
  40. /*
  41. * get_sdr_cs_offset -
  42. * - Get offset of cs from cs0 start
  43. */
  44. u32 get_sdr_cs_offset(u32 cs)
  45. {
  46. u32 offset = 0;
  47. return offset;
  48. }
  49. /*
  50. * do_emif4_init -
  51. * - Init the emif4 module for DDR access
  52. * - Early init routines, called from flash or SRAM.
  53. */
  54. static void do_emif4_init(void)
  55. {
  56. unsigned int regval;
  57. /* Set the DDR PHY parameters in PHY ctrl registers */
  58. regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
  59. EMIF4_DDR1_EXT_STRB_DIS);
  60. writel(regval, &emif4_base->ddr_phyctrl1);
  61. writel(regval, &emif4_base->ddr_phyctrl1_shdw);
  62. writel(0, &emif4_base->ddr_phyctrl2);
  63. /* Reset the DDR PHY and wait till completed */
  64. regval = readl(&emif4_base->sdram_iodft_tlgc);
  65. regval |= (1<<10);
  66. writel(regval, &emif4_base->sdram_iodft_tlgc);
  67. /*Wait till that bit clears*/
  68. while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0);
  69. /*Re-verify the DDR PHY status*/
  70. while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
  71. regval |= (1<<0);
  72. writel(regval, &emif4_base->sdram_iodft_tlgc);
  73. /* Set SDR timing registers */
  74. regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
  75. EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
  76. EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
  77. EMIF4_TIM1_T_RP);
  78. writel(regval, &emif4_base->sdram_time1);
  79. writel(regval, &emif4_base->sdram_time1_shdw);
  80. regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
  81. EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
  82. EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
  83. writel(regval, &emif4_base->sdram_time2);
  84. writel(regval, &emif4_base->sdram_time2_shdw);
  85. regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
  86. writel(regval, &emif4_base->sdram_time3);
  87. writel(regval, &emif4_base->sdram_time3_shdw);
  88. /* Set the PWR control register */
  89. regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
  90. EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
  91. writel(regval, &emif4_base->sdram_pwr_mgmt);
  92. writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
  93. /* Set the DDR refresh rate control register */
  94. regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
  95. writel(regval, &emif4_base->sdram_refresh_ctrl);
  96. writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
  97. /* set the SDRAM configuration register */
  98. regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
  99. EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
  100. EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
  101. EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
  102. EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
  103. EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
  104. writel(regval, &emif4_base->sdram_config);
  105. }
  106. /*
  107. * dram_init -
  108. * - Sets uboots idea of sdram size
  109. */
  110. int dram_init(void)
  111. {
  112. unsigned int size0 = 0, size1 = 0;
  113. size0 = get_sdr_cs_size(CS0);
  114. /*
  115. * If a second bank of DDR is attached to CS1 this is
  116. * where it can be started. Early init code will init
  117. * memory on CS0.
  118. */
  119. if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
  120. size1 = get_sdr_cs_size(CS1);
  121. gd->ram_size = size0 + size1;
  122. return 0;
  123. }
  124. int dram_init_banksize(void)
  125. {
  126. unsigned int size0 = 0, size1 = 0;
  127. size0 = get_sdr_cs_size(CS0);
  128. size1 = get_sdr_cs_size(CS1);
  129. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  130. gd->bd->bi_dram[0].size = size0;
  131. gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
  132. gd->bd->bi_dram[1].size = size1;
  133. return 0;
  134. }
  135. /*
  136. * mem_init() -
  137. * - Initialize memory subsystem
  138. */
  139. void mem_init(void)
  140. {
  141. do_emif4_init();
  142. }