clocks-common.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Clock initialization for OMAP4
  5. *
  6. * (C) Copyright 2010
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Aneesh V <aneesh@ti.com>
  10. *
  11. * Based on previous work by:
  12. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  13. * Rajendra Nayak <rnayak@ti.com>
  14. */
  15. #include <common.h>
  16. #include <hang.h>
  17. #include <i2c.h>
  18. #include <init.h>
  19. #include <asm/omap_common.h>
  20. #include <asm/gpio.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/utils.h>
  24. #include <asm/omap_gpio.h>
  25. #include <asm/emif.h>
  26. #ifndef CONFIG_SPL_BUILD
  27. /*
  28. * printing to console doesn't work unless
  29. * this code is executed from SPL
  30. */
  31. #define printf(fmt, args...)
  32. #define puts(s)
  33. #endif
  34. const u32 sys_clk_array[8] = {
  35. 12000000, /* 12 MHz */
  36. 20000000, /* 20 MHz */
  37. 16800000, /* 16.8 MHz */
  38. 19200000, /* 19.2 MHz */
  39. 26000000, /* 26 MHz */
  40. 27000000, /* 27 MHz */
  41. 38400000, /* 38.4 MHz */
  42. };
  43. static inline u32 __get_sys_clk_index(void)
  44. {
  45. s8 ind;
  46. /*
  47. * For ES1 the ROM code calibration of sys clock is not reliable
  48. * due to hw issue. So, use hard-coded value. If this value is not
  49. * correct for any board over-ride this function in board file
  50. * From ES2.0 onwards you will get this information from
  51. * CM_SYS_CLKSEL
  52. */
  53. if (omap_revision() == OMAP4430_ES1_0)
  54. ind = OMAP_SYS_CLK_IND_38_4_MHZ;
  55. else {
  56. /* SYS_CLKSEL - 1 to match the dpll param array indices */
  57. ind = (readl((*prcm)->cm_sys_clksel) &
  58. CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
  59. }
  60. return ind;
  61. }
  62. u32 get_sys_clk_index(void)
  63. __attribute__ ((weak, alias("__get_sys_clk_index")));
  64. u32 get_sys_clk_freq(void)
  65. {
  66. u8 index = get_sys_clk_index();
  67. return sys_clk_array[index];
  68. }
  69. void setup_post_dividers(u32 const base, const struct dpll_params *params)
  70. {
  71. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  72. /* Setup post-dividers */
  73. if (params->m2 >= 0)
  74. writel(params->m2, &dpll_regs->cm_div_m2_dpll);
  75. if (params->m3 >= 0)
  76. writel(params->m3, &dpll_regs->cm_div_m3_dpll);
  77. if (params->m4_h11 >= 0)
  78. writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
  79. if (params->m5_h12 >= 0)
  80. writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
  81. if (params->m6_h13 >= 0)
  82. writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
  83. if (params->m7_h14 >= 0)
  84. writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
  85. if (params->h21 >= 0)
  86. writel(params->h21, &dpll_regs->cm_div_h21_dpll);
  87. if (params->h22 >= 0)
  88. writel(params->h22, &dpll_regs->cm_div_h22_dpll);
  89. if (params->h23 >= 0)
  90. writel(params->h23, &dpll_regs->cm_div_h23_dpll);
  91. if (params->h24 >= 0)
  92. writel(params->h24, &dpll_regs->cm_div_h24_dpll);
  93. }
  94. static inline void do_bypass_dpll(u32 const base)
  95. {
  96. struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
  97. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  98. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  99. DPLL_EN_FAST_RELOCK_BYPASS <<
  100. CM_CLKMODE_DPLL_EN_SHIFT);
  101. }
  102. static inline void wait_for_bypass(u32 const base)
  103. {
  104. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  105. if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
  106. LDELAY)) {
  107. printf("Bypassing DPLL failed %x\n", base);
  108. }
  109. }
  110. static inline void do_lock_dpll(u32 const base)
  111. {
  112. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  113. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  114. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  115. DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
  116. }
  117. static inline void wait_for_lock(u32 const base)
  118. {
  119. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  120. if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
  121. &dpll_regs->cm_idlest_dpll, LDELAY)) {
  122. printf("DPLL locking failed for %x\n", base);
  123. hang();
  124. }
  125. }
  126. inline u32 check_for_lock(u32 const base)
  127. {
  128. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  129. u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
  130. return lock;
  131. }
  132. const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
  133. {
  134. u32 sysclk_ind = get_sys_clk_index();
  135. return &dpll_data->mpu[sysclk_ind];
  136. }
  137. const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
  138. {
  139. u32 sysclk_ind = get_sys_clk_index();
  140. return &dpll_data->core[sysclk_ind];
  141. }
  142. const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
  143. {
  144. u32 sysclk_ind = get_sys_clk_index();
  145. return &dpll_data->per[sysclk_ind];
  146. }
  147. const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
  148. {
  149. u32 sysclk_ind = get_sys_clk_index();
  150. return &dpll_data->iva[sysclk_ind];
  151. }
  152. const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
  153. {
  154. u32 sysclk_ind = get_sys_clk_index();
  155. return &dpll_data->usb[sysclk_ind];
  156. }
  157. const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
  158. {
  159. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  160. u32 sysclk_ind = get_sys_clk_index();
  161. return &dpll_data->abe[sysclk_ind];
  162. #else
  163. return dpll_data->abe;
  164. #endif
  165. }
  166. static const struct dpll_params *get_ddr_dpll_params
  167. (struct dplls const *dpll_data)
  168. {
  169. u32 sysclk_ind = get_sys_clk_index();
  170. if (!dpll_data->ddr)
  171. return NULL;
  172. return &dpll_data->ddr[sysclk_ind];
  173. }
  174. #ifdef CONFIG_DRIVER_TI_CPSW
  175. static const struct dpll_params *get_gmac_dpll_params
  176. (struct dplls const *dpll_data)
  177. {
  178. u32 sysclk_ind = get_sys_clk_index();
  179. if (!dpll_data->gmac)
  180. return NULL;
  181. return &dpll_data->gmac[sysclk_ind];
  182. }
  183. #endif
  184. static void do_setup_dpll(u32 const base, const struct dpll_params *params,
  185. u8 lock, char *dpll)
  186. {
  187. u32 temp, M, N;
  188. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  189. if (!params)
  190. return;
  191. temp = readl(&dpll_regs->cm_clksel_dpll);
  192. if (check_for_lock(base)) {
  193. /*
  194. * The Dpll has already been locked by rom code using CH.
  195. * Check if M,N are matching with Ideal nominal opp values.
  196. * If matches, skip the rest otherwise relock.
  197. */
  198. M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
  199. N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
  200. if ((M != (params->m)) || (N != (params->n))) {
  201. debug("\n %s Dpll locked, but not for ideal M = %d,"
  202. "N = %d values, current values are M = %d,"
  203. "N= %d" , dpll, params->m, params->n,
  204. M, N);
  205. } else {
  206. /* Dpll locked with ideal values for nominal opps. */
  207. debug("\n %s Dpll already locked with ideal"
  208. "nominal opp values", dpll);
  209. bypass_dpll(base);
  210. goto setup_post_dividers;
  211. }
  212. }
  213. bypass_dpll(base);
  214. /* Set M & N */
  215. temp &= ~CM_CLKSEL_DPLL_M_MASK;
  216. temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
  217. temp &= ~CM_CLKSEL_DPLL_N_MASK;
  218. temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
  219. writel(temp, &dpll_regs->cm_clksel_dpll);
  220. setup_post_dividers:
  221. setup_post_dividers(base, params);
  222. /* Lock */
  223. if (lock)
  224. do_lock_dpll(base);
  225. /* Wait till the DPLL locks */
  226. if (lock)
  227. wait_for_lock(base);
  228. }
  229. u32 omap_ddr_clk(void)
  230. {
  231. u32 ddr_clk, sys_clk_khz, omap_rev, divider;
  232. const struct dpll_params *core_dpll_params;
  233. omap_rev = omap_revision();
  234. sys_clk_khz = get_sys_clk_freq() / 1000;
  235. core_dpll_params = get_core_dpll_params(*dplls_data);
  236. debug("sys_clk %d\n ", sys_clk_khz * 1000);
  237. /* Find Core DPLL locked frequency first */
  238. ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
  239. (core_dpll_params->n + 1);
  240. if (omap_rev < OMAP5430_ES1_0) {
  241. /*
  242. * DDR frequency is PHY_ROOT_CLK/2
  243. * PHY_ROOT_CLK = Fdpll/2/M2
  244. */
  245. divider = 4;
  246. } else {
  247. /*
  248. * DDR frequency is PHY_ROOT_CLK
  249. * PHY_ROOT_CLK = Fdpll/2/M2
  250. */
  251. divider = 2;
  252. }
  253. ddr_clk = ddr_clk / divider / core_dpll_params->m2;
  254. ddr_clk *= 1000; /* convert to Hz */
  255. debug("ddr_clk %d\n ", ddr_clk);
  256. return ddr_clk;
  257. }
  258. /*
  259. * Lock MPU dpll
  260. *
  261. * Resulting MPU frequencies:
  262. * 4430 ES1.0 : 600 MHz
  263. * 4430 ES2.x : 792 MHz (OPP Turbo)
  264. * 4460 : 920 MHz (OPP Turbo) - DCC disabled
  265. */
  266. void configure_mpu_dpll(void)
  267. {
  268. const struct dpll_params *params;
  269. struct dpll_regs *mpu_dpll_regs;
  270. u32 omap_rev;
  271. omap_rev = omap_revision();
  272. /*
  273. * DCC and clock divider settings for 4460.
  274. * DCC is required, if more than a certain frequency is required.
  275. * For, 4460 > 1GHZ.
  276. * 5430 > 1.4GHZ.
  277. */
  278. if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
  279. mpu_dpll_regs =
  280. (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
  281. bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
  282. clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  283. MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
  284. setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  285. MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
  286. clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
  287. CM_CLKSEL_DCC_EN_MASK);
  288. }
  289. params = get_mpu_dpll_params(*dplls_data);
  290. do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
  291. debug("MPU DPLL locked\n");
  292. }
  293. #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
  294. defined(CONFIG_USB_MUSB_OMAP2PLUS)
  295. static void setup_usb_dpll(void)
  296. {
  297. const struct dpll_params *params;
  298. u32 sys_clk_khz, sd_div, num, den;
  299. sys_clk_khz = get_sys_clk_freq() / 1000;
  300. /*
  301. * USB:
  302. * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
  303. * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
  304. * - where CLKINP is sys_clk in MHz
  305. * Use CLKINP in KHz and adjust the denominator accordingly so
  306. * that we have enough accuracy and at the same time no overflow
  307. */
  308. params = get_usb_dpll_params(*dplls_data);
  309. num = params->m * sys_clk_khz;
  310. den = (params->n + 1) * 250 * 1000;
  311. num += den - 1;
  312. sd_div = num / den;
  313. clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
  314. CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
  315. sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
  316. /* Now setup the dpll with the regular function */
  317. do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
  318. }
  319. #endif
  320. static void setup_dplls(void)
  321. {
  322. u32 temp;
  323. const struct dpll_params *params;
  324. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  325. debug("setup_dplls\n");
  326. /* CORE dpll */
  327. params = get_core_dpll_params(*dplls_data); /* default - safest */
  328. /*
  329. * Do not lock the core DPLL now. Just set it up.
  330. * Core DPLL will be locked after setting up EMIF
  331. * using the FREQ_UPDATE method(freq_update_core())
  332. */
  333. if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
  334. EMIF_SDRAM_TYPE_LPDDR2)
  335. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  336. DPLL_NO_LOCK, "core");
  337. else
  338. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  339. DPLL_LOCK, "core");
  340. /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
  341. temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
  342. (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
  343. (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
  344. writel(temp, (*prcm)->cm_clksel_core);
  345. debug("Core DPLL configured\n");
  346. /* lock PER dpll */
  347. params = get_per_dpll_params(*dplls_data);
  348. do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
  349. params, DPLL_LOCK, "per");
  350. debug("PER DPLL locked\n");
  351. /* MPU dpll */
  352. configure_mpu_dpll();
  353. #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
  354. defined(CONFIG_USB_MUSB_OMAP2PLUS)
  355. setup_usb_dpll();
  356. #endif
  357. params = get_ddr_dpll_params(*dplls_data);
  358. do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
  359. params, DPLL_LOCK, "ddr");
  360. #ifdef CONFIG_DRIVER_TI_CPSW
  361. params = get_gmac_dpll_params(*dplls_data);
  362. do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
  363. DPLL_LOCK, "gmac");
  364. #endif
  365. }
  366. u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
  367. {
  368. u32 offset_code;
  369. volt_offset -= pmic->base_offset;
  370. offset_code = (volt_offset + pmic->step - 1) / pmic->step;
  371. /*
  372. * Offset codes 1-6 all give the base voltage in Palmas
  373. * Offset code 0 switches OFF the SMPS
  374. */
  375. return offset_code + pmic->start_code;
  376. }
  377. void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
  378. {
  379. u32 offset_code;
  380. u32 offset = volt_mv;
  381. int ret = 0;
  382. if (!volt_mv)
  383. return;
  384. pmic->pmic_bus_init();
  385. /* See if we can first get the GPIO if needed */
  386. if (pmic->gpio_en)
  387. ret = gpio_request(pmic->gpio, "PMIC_GPIO");
  388. if (ret < 0) {
  389. printf("%s: gpio %d request failed %d\n", __func__,
  390. pmic->gpio, ret);
  391. return;
  392. }
  393. /* Pull the GPIO low to select SET0 register, while we program SET1 */
  394. if (pmic->gpio_en)
  395. gpio_direction_output(pmic->gpio, 0);
  396. /* convert to uV for better accuracy in the calculations */
  397. offset *= 1000;
  398. offset_code = get_offset_code(offset, pmic);
  399. debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
  400. offset_code);
  401. if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
  402. printf("Scaling voltage failed for 0x%x\n", vcore_reg);
  403. if (pmic->gpio_en)
  404. gpio_direction_output(pmic->gpio, 1);
  405. }
  406. int __weak get_voltrail_opp(int rail_offset)
  407. {
  408. /*
  409. * By default return OPP_NOM for all voltage rails.
  410. */
  411. return OPP_NOM;
  412. }
  413. static u32 optimize_vcore_voltage(struct volts const *v, int opp)
  414. {
  415. u32 val;
  416. if (!v->value[opp])
  417. return 0;
  418. if (!v->efuse.reg[opp])
  419. return v->value[opp];
  420. switch (v->efuse.reg_bits) {
  421. case 16:
  422. val = readw(v->efuse.reg[opp]);
  423. break;
  424. case 32:
  425. val = readl(v->efuse.reg[opp]);
  426. break;
  427. default:
  428. printf("Error: efuse 0x%08x bits=%d unknown\n",
  429. v->efuse.reg[opp], v->efuse.reg_bits);
  430. return v->value[opp];
  431. }
  432. if (!val) {
  433. printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
  434. v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
  435. return v->value[opp];
  436. }
  437. debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
  438. __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
  439. val);
  440. return val;
  441. }
  442. #ifdef CONFIG_IODELAY_RECALIBRATION
  443. void __weak recalibrate_iodelay(void)
  444. {
  445. }
  446. #endif
  447. /*
  448. * Setup the voltages for the main SoC core power domains.
  449. * We start with the maximum voltages allowed here, as set in the corresponding
  450. * vcores_data struct, and then scale (usually down) to the fused values that
  451. * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
  452. * are initialised.
  453. * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
  454. * compiled conditionally. Note that the new code writes the scaled (or zeroed)
  455. * values back to the vcores_data struct for eventual reuse. Zero values mean
  456. * that the corresponding rails are not controlled separately, and are not sent
  457. * to the PMIC.
  458. */
  459. void scale_vcores(struct vcores_data const *vcores)
  460. {
  461. int i, opp, j, ol;
  462. struct volts *pv = (struct volts *)vcores;
  463. struct volts *px;
  464. for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
  465. opp = get_voltrail_opp(i);
  466. debug("%d -> ", pv->value[opp]);
  467. if (pv->value[opp]) {
  468. /* Handle non-empty members only */
  469. pv->value[opp] = optimize_vcore_voltage(pv, opp);
  470. px = (struct volts *)vcores;
  471. j = 0;
  472. while (px < pv) {
  473. /*
  474. * Scan already handled non-empty members to see
  475. * if we have a group and find the max voltage,
  476. * which is set to the first occurance of the
  477. * particular SMPS; the other group voltages are
  478. * zeroed.
  479. */
  480. ol = get_voltrail_opp(j);
  481. if (px->value[ol] &&
  482. (pv->pmic->i2c_slave_addr ==
  483. px->pmic->i2c_slave_addr) &&
  484. (pv->addr == px->addr)) {
  485. /* Same PMIC, same SMPS */
  486. if (pv->value[opp] > px->value[ol])
  487. px->value[ol] = pv->value[opp];
  488. pv->value[opp] = 0;
  489. }
  490. px++;
  491. j++;
  492. }
  493. }
  494. debug("%d\n", pv->value[opp]);
  495. pv++;
  496. }
  497. opp = get_voltrail_opp(VOLT_CORE);
  498. debug("cor: %d\n", vcores->core.value[opp]);
  499. do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
  500. vcores->core.pmic);
  501. /*
  502. * IO delay recalibration should be done immediately after
  503. * adjusting AVS voltages for VDD_CORE_L.
  504. * Respective boards should call __recalibrate_iodelay()
  505. * with proper mux, virtual and manual mode configurations.
  506. */
  507. #ifdef CONFIG_IODELAY_RECALIBRATION
  508. recalibrate_iodelay();
  509. #endif
  510. opp = get_voltrail_opp(VOLT_MPU);
  511. debug("mpu: %d\n", vcores->mpu.value[opp]);
  512. do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
  513. vcores->mpu.pmic);
  514. /* Configure MPU ABB LDO after scale */
  515. abb_setup(vcores->mpu.efuse.reg[opp],
  516. (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
  517. (*prcm)->prm_abbldo_mpu_setup,
  518. (*prcm)->prm_abbldo_mpu_ctrl,
  519. (*prcm)->prm_irqstatus_mpu_2,
  520. vcores->mpu.abb_tx_done_mask,
  521. OMAP_ABB_FAST_OPP);
  522. opp = get_voltrail_opp(VOLT_MM);
  523. debug("mm: %d\n", vcores->mm.value[opp]);
  524. do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
  525. vcores->mm.pmic);
  526. /* Configure MM ABB LDO after scale */
  527. abb_setup(vcores->mm.efuse.reg[opp],
  528. (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
  529. (*prcm)->prm_abbldo_mm_setup,
  530. (*prcm)->prm_abbldo_mm_ctrl,
  531. (*prcm)->prm_irqstatus_mpu,
  532. vcores->mm.abb_tx_done_mask,
  533. OMAP_ABB_FAST_OPP);
  534. opp = get_voltrail_opp(VOLT_GPU);
  535. debug("gpu: %d\n", vcores->gpu.value[opp]);
  536. do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
  537. vcores->gpu.pmic);
  538. /* Configure GPU ABB LDO after scale */
  539. abb_setup(vcores->gpu.efuse.reg[opp],
  540. (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
  541. (*prcm)->prm_abbldo_gpu_setup,
  542. (*prcm)->prm_abbldo_gpu_ctrl,
  543. (*prcm)->prm_irqstatus_mpu,
  544. vcores->gpu.abb_tx_done_mask,
  545. OMAP_ABB_FAST_OPP);
  546. opp = get_voltrail_opp(VOLT_EVE);
  547. debug("eve: %d\n", vcores->eve.value[opp]);
  548. do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
  549. vcores->eve.pmic);
  550. /* Configure EVE ABB LDO after scale */
  551. abb_setup(vcores->eve.efuse.reg[opp],
  552. (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
  553. (*prcm)->prm_abbldo_eve_setup,
  554. (*prcm)->prm_abbldo_eve_ctrl,
  555. (*prcm)->prm_irqstatus_mpu,
  556. vcores->eve.abb_tx_done_mask,
  557. OMAP_ABB_FAST_OPP);
  558. opp = get_voltrail_opp(VOLT_IVA);
  559. debug("iva: %d\n", vcores->iva.value[opp]);
  560. do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
  561. vcores->iva.pmic);
  562. /* Configure IVA ABB LDO after scale */
  563. abb_setup(vcores->iva.efuse.reg[opp],
  564. (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
  565. (*prcm)->prm_abbldo_iva_setup,
  566. (*prcm)->prm_abbldo_iva_ctrl,
  567. (*prcm)->prm_irqstatus_mpu,
  568. vcores->iva.abb_tx_done_mask,
  569. OMAP_ABB_FAST_OPP);
  570. }
  571. static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
  572. {
  573. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  574. enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
  575. debug("Enable clock domain - %x\n", clkctrl_reg);
  576. }
  577. static inline void disable_clock_domain(u32 const clkctrl_reg)
  578. {
  579. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  580. CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
  581. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  582. debug("Disable clock domain - %x\n", clkctrl_reg);
  583. }
  584. static inline void wait_for_clk_enable(u32 clkctrl_addr)
  585. {
  586. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
  587. u32 bound = LDELAY;
  588. while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
  589. (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
  590. clkctrl = readl(clkctrl_addr);
  591. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  592. MODULE_CLKCTRL_IDLEST_SHIFT;
  593. if (--bound == 0) {
  594. printf("Clock enable failed for 0x%x idlest 0x%x\n",
  595. clkctrl_addr, clkctrl);
  596. return;
  597. }
  598. }
  599. }
  600. static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
  601. u32 wait_for_enable)
  602. {
  603. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  604. enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
  605. debug("Enable clock module - %x\n", clkctrl_addr);
  606. if (wait_for_enable)
  607. wait_for_clk_enable(clkctrl_addr);
  608. }
  609. static inline void wait_for_clk_disable(u32 clkctrl_addr)
  610. {
  611. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
  612. u32 bound = LDELAY;
  613. while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
  614. clkctrl = readl(clkctrl_addr);
  615. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  616. MODULE_CLKCTRL_IDLEST_SHIFT;
  617. if (--bound == 0) {
  618. printf("Clock disable failed for 0x%x idlest 0x%x\n",
  619. clkctrl_addr, clkctrl);
  620. return;
  621. }
  622. }
  623. }
  624. static inline void disable_clock_module(u32 const clkctrl_addr,
  625. u32 wait_for_disable)
  626. {
  627. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  628. MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
  629. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  630. debug("Disable clock module - %x\n", clkctrl_addr);
  631. if (wait_for_disable)
  632. wait_for_clk_disable(clkctrl_addr);
  633. }
  634. void freq_update_core(void)
  635. {
  636. u32 freq_config1 = 0;
  637. const struct dpll_params *core_dpll_params;
  638. u32 omap_rev = omap_revision();
  639. core_dpll_params = get_core_dpll_params(*dplls_data);
  640. /* Put EMIF clock domain in sw wakeup mode */
  641. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  642. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  643. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  644. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  645. freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
  646. SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
  647. freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
  648. SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
  649. freq_config1 |= (core_dpll_params->m2 <<
  650. SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
  651. SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
  652. writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
  653. if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
  654. (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
  655. puts("FREQ UPDATE procedure failed!!");
  656. hang();
  657. }
  658. /*
  659. * Putting EMIF in HW_AUTO is seen to be causing issues with
  660. * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
  661. * in OMAP5430 ES1.0 silicon
  662. */
  663. if (omap_rev != OMAP5430_ES1_0) {
  664. /* Put EMIF clock domain back in hw auto mode */
  665. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  666. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  667. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  668. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  669. }
  670. }
  671. void bypass_dpll(u32 const base)
  672. {
  673. do_bypass_dpll(base);
  674. wait_for_bypass(base);
  675. }
  676. void lock_dpll(u32 const base)
  677. {
  678. do_lock_dpll(base);
  679. wait_for_lock(base);
  680. }
  681. static void setup_clocks_for_console(void)
  682. {
  683. /* Do not add any spl_debug prints in this function */
  684. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  685. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  686. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  687. /* Enable all UARTs - console will be on one of them */
  688. clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
  689. MODULE_CLKCTRL_MODULEMODE_MASK,
  690. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  691. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  692. clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
  693. MODULE_CLKCTRL_MODULEMODE_MASK,
  694. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  695. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  696. clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
  697. MODULE_CLKCTRL_MODULEMODE_MASK,
  698. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  699. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  700. clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
  701. MODULE_CLKCTRL_MODULEMODE_MASK,
  702. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  703. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  704. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  705. CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
  706. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  707. }
  708. void do_enable_clocks(u32 const *clk_domains,
  709. u32 const *clk_modules_hw_auto,
  710. u32 const *clk_modules_explicit_en,
  711. u8 wait_for_enable)
  712. {
  713. u32 i, max = 100;
  714. /* Put the clock domains in SW_WKUP mode */
  715. for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
  716. enable_clock_domain(clk_domains[i],
  717. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  718. }
  719. /* Clock modules that need to be put in HW_AUTO */
  720. for (i = 0; (i < max) && clk_modules_hw_auto &&
  721. clk_modules_hw_auto[i]; i++) {
  722. enable_clock_module(clk_modules_hw_auto[i],
  723. MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
  724. wait_for_enable);
  725. };
  726. /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
  727. for (i = 0; (i < max) && clk_modules_explicit_en &&
  728. clk_modules_explicit_en[i]; i++) {
  729. enable_clock_module(clk_modules_explicit_en[i],
  730. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
  731. wait_for_enable);
  732. };
  733. /* Put the clock domains in HW_AUTO mode now */
  734. for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
  735. enable_clock_domain(clk_domains[i],
  736. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  737. }
  738. }
  739. void do_disable_clocks(u32 const *clk_domains,
  740. u32 const *clk_modules_disable,
  741. u8 wait_for_disable)
  742. {
  743. u32 i, max = 100;
  744. /* Clock modules that need to be put in SW_DISABLE */
  745. for (i = 0; (i < max) && clk_modules_disable[i]; i++)
  746. disable_clock_module(clk_modules_disable[i],
  747. wait_for_disable);
  748. /* Put the clock domains in SW_SLEEP mode */
  749. for (i = 0; (i < max) && clk_domains[i]; i++)
  750. disable_clock_domain(clk_domains[i]);
  751. }
  752. /**
  753. * setup_early_clocks() - Setup early clocks needed for SoC
  754. *
  755. * Setup clocks for console, SPL basic initialization clocks and initialize
  756. * the timer. This is invoked prior prcm_init.
  757. */
  758. void setup_early_clocks(void)
  759. {
  760. switch (omap_hw_init_context()) {
  761. case OMAP_INIT_CONTEXT_SPL:
  762. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  763. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  764. setup_clocks_for_console();
  765. enable_basic_clocks();
  766. timer_init();
  767. /* Fall through */
  768. }
  769. }
  770. void prcm_init(void)
  771. {
  772. switch (omap_hw_init_context()) {
  773. case OMAP_INIT_CONTEXT_SPL:
  774. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  775. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  776. scale_vcores(*omap_vcores);
  777. setup_dplls();
  778. setup_warmreset_time();
  779. break;
  780. default:
  781. break;
  782. }
  783. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
  784. enable_basic_uboot_clocks();
  785. }
  786. #if !defined(CONFIG_DM_I2C)
  787. void gpi2c_init(void)
  788. {
  789. static int gpi2c = 1;
  790. if (gpi2c) {
  791. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  792. CONFIG_SYS_OMAP24_I2C_SLAVE);
  793. gpi2c = 0;
  794. }
  795. }
  796. #endif