sys_info.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sys_info.c
  4. *
  5. * System information functions
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. *
  9. * Derived from Beagle Board and 3430 SDP code by
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <init.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/clock.h>
  19. #include <power/tps65910.h>
  20. #include <linux/compiler.h>
  21. struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
  22. /**
  23. * get_cpu_rev(void) - extract rev info
  24. */
  25. u32 get_cpu_rev(void)
  26. {
  27. u32 id;
  28. u32 rev;
  29. id = readl(DEVICE_ID);
  30. rev = (id >> 28) & 0xff;
  31. return rev;
  32. }
  33. /**
  34. * get_cpu_type(void) - extract cpu info
  35. */
  36. u32 get_cpu_type(void)
  37. {
  38. u32 id = 0;
  39. u32 partnum;
  40. id = readl(DEVICE_ID);
  41. partnum = (id >> 12) & 0xffff;
  42. return partnum;
  43. }
  44. /**
  45. * get_sysboot_value(void) - return SYS_BOOT[4:0]
  46. */
  47. u32 get_sysboot_value(void)
  48. {
  49. return readl(&cstat->statusreg) & SYSBOOT_MASK;
  50. }
  51. u32 get_sys_clk_index(void)
  52. {
  53. struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
  54. u32 ind = readl(&ctrl->statusreg);
  55. #ifdef CONFIG_AM43XX
  56. u32 src;
  57. src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
  58. if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
  59. return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
  60. CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
  61. else /* Value read from SYS BOOT pins */
  62. #endif
  63. return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
  64. CTRL_SYSBOOT_15_14_SHIFT);
  65. }
  66. #ifdef CONFIG_DISPLAY_CPUINFO
  67. static char *cpu_revs[] = {
  68. "1.0",
  69. "2.0",
  70. "2.1"};
  71. static char *cpu_revs_am43xx[] = {
  72. "1.0",
  73. "1.1",
  74. "1.2"};
  75. static char *dev_types[] = {
  76. "TST",
  77. "EMU",
  78. "HS",
  79. "GP"};
  80. /**
  81. * Print CPU information
  82. */
  83. int print_cpuinfo(void)
  84. {
  85. char *cpu_s, *sec_s, *rev_s;
  86. char **cpu_rev_arr = cpu_revs;
  87. switch (get_cpu_type()) {
  88. case AM335X:
  89. cpu_s = "AM335X";
  90. break;
  91. case TI81XX:
  92. cpu_s = "TI81XX";
  93. break;
  94. case AM437X:
  95. cpu_s = "AM437X";
  96. cpu_rev_arr = cpu_revs_am43xx;
  97. break;
  98. default:
  99. cpu_s = "Unknown CPU type";
  100. break;
  101. }
  102. if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
  103. rev_s = cpu_rev_arr[get_cpu_rev()];
  104. else
  105. rev_s = "?";
  106. if (get_device_type() < ARRAY_SIZE(dev_types))
  107. sec_s = dev_types[get_device_type()];
  108. else
  109. sec_s = "?";
  110. printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
  111. return 0;
  112. }
  113. #endif /* CONFIG_DISPLAY_CPUINFO */
  114. #ifdef CONFIG_AM33XX
  115. int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
  116. {
  117. int sil_rev;
  118. sil_rev = readl(&cdev->deviceid) >> 28;
  119. if (sil_rev == 0) {
  120. /* No efuse in PG 1.0. Use max speed */
  121. return MPUPLL_M_720;
  122. } else if (sil_rev >= 1) {
  123. /* Check what the efuse says our max speed is. */
  124. int efuse_arm_mpu_max_freq, package_type;
  125. efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
  126. package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
  127. PACKAGE_TYPE_SHIFT;
  128. /* PG 2.0, efuse may not be set. */
  129. if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
  130. PACKAGE_TYPE_RESERVED)
  131. return MPUPLL_M_800;
  132. switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
  133. case AM335X_ZCZ_1000:
  134. return MPUPLL_M_1000;
  135. case AM335X_ZCZ_800:
  136. return MPUPLL_M_800;
  137. case AM335X_ZCZ_720:
  138. return MPUPLL_M_720;
  139. case AM335X_ZCZ_600:
  140. case AM335X_ZCE_600:
  141. return MPUPLL_M_600;
  142. case AM335X_ZCZ_300:
  143. case AM335X_ZCE_300:
  144. return MPUPLL_M_300;
  145. }
  146. }
  147. /* unknown, use the PG1.0 max */
  148. return MPUPLL_M_720;
  149. }
  150. int am335x_get_mpu_vdd(int sil_rev, int frequency)
  151. {
  152. int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
  153. switch (sel_mask) {
  154. case TPS65910_OP_REG_SEL_1_3_2_5:
  155. return 1325000;
  156. case TPS65910_OP_REG_SEL_1_2_0:
  157. return 1200000;
  158. case TPS65910_OP_REG_SEL_1_1_0:
  159. return 1100000;
  160. default:
  161. return 1262500;
  162. }
  163. }
  164. int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
  165. {
  166. /* For PG2.0 and later, we have one set of values. */
  167. if (sil_rev >= 1) {
  168. switch (frequency) {
  169. case MPUPLL_M_1000:
  170. return TPS65910_OP_REG_SEL_1_3_2_5;
  171. case MPUPLL_M_800:
  172. return TPS65910_OP_REG_SEL_1_2_6;
  173. case MPUPLL_M_720:
  174. return TPS65910_OP_REG_SEL_1_2_0;
  175. case MPUPLL_M_600:
  176. case MPUPLL_M_500:
  177. case MPUPLL_M_300:
  178. return TPS65910_OP_REG_SEL_1_1_0;
  179. }
  180. }
  181. /* Default to PG1.0 values. */
  182. return TPS65910_OP_REG_SEL_1_2_6;
  183. }
  184. #endif