init.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Copyright (C) 2019 BayLibre, SAS
  5. * Author: Fabien Parent <fparent@baylibre.com>
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <init.h>
  13. #include <ram.h>
  14. #include <asm/arch/misc.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <asm/cache.h>
  17. #include <asm/sections.h>
  18. #include <dm/uclass.h>
  19. #include <dt-bindings/clock/mt8516-clk.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int dram_init(void)
  22. {
  23. int ret;
  24. ret = fdtdec_setup_memory_banksize();
  25. if (ret)
  26. return ret;
  27. return fdtdec_setup_mem_size_base();
  28. }
  29. int dram_init_banksize(void)
  30. {
  31. gd->bd->bi_dram[0].start = gd->ram_base;
  32. gd->bd->bi_dram[0].size = gd->ram_size;
  33. return 0;
  34. }
  35. int mtk_pll_early_init(void)
  36. {
  37. unsigned long pll_rates[] = {
  38. [CLK_APMIXED_ARMPLL] = 1300000000,
  39. [CLK_APMIXED_MAINPLL] = 1501000000,
  40. [CLK_APMIXED_UNIVPLL] = 1248000000,
  41. [CLK_APMIXED_MMPLL] = 380000000,
  42. };
  43. struct udevice *dev;
  44. int ret, i;
  45. ret = uclass_get_device_by_driver(UCLASS_CLK,
  46. DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  47. if (ret)
  48. return ret;
  49. /* configure default rate then enable apmixedsys */
  50. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  51. struct clk clk = { .id = i, .dev = dev };
  52. ret = clk_set_rate(&clk, pll_rates[i]);
  53. if (ret)
  54. return ret;
  55. ret = clk_enable(&clk);
  56. if (ret)
  57. return ret;
  58. }
  59. return 0;
  60. }
  61. int mtk_soc_early_init(void)
  62. {
  63. int ret;
  64. /* initialize early clocks */
  65. ret = mtk_pll_early_init();
  66. if (ret)
  67. return ret;
  68. return 0;
  69. }
  70. void reset_cpu(ulong addr)
  71. {
  72. psci_system_reset();
  73. }
  74. int print_cpuinfo(void)
  75. {
  76. printf("CPU: MediaTek MT8516\n");
  77. return 0;
  78. }
  79. static struct mm_region mt8516_mem_map[] = {
  80. {
  81. /* DDR */
  82. .virt = 0x40000000UL,
  83. .phys = 0x40000000UL,
  84. .size = 0x20000000UL,
  85. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  86. }, {
  87. .virt = 0x00000000UL,
  88. .phys = 0x00000000UL,
  89. .size = 0x20000000UL,
  90. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  91. PTE_BLOCK_NON_SHARE |
  92. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  93. }, {
  94. 0,
  95. }
  96. };
  97. struct mm_region *mem_map = mt8516_mem_map;