cpu.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <cpu_func.h>
  10. #include <env.h>
  11. #include <init.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/soc.h>
  18. #include <mvebu_mmc.h>
  19. void reset_cpu(unsigned long ignored)
  20. {
  21. struct kwcpu_registers *cpureg =
  22. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  23. writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  24. &cpureg->rstoutn_mask);
  25. writel(readl(&cpureg->sys_soft_rst) | 1,
  26. &cpureg->sys_soft_rst);
  27. while (1) ;
  28. }
  29. /*
  30. * Window Size
  31. * Used with the Base register to set the address window size and location.
  32. * Must be programmed from LSB to MSB as sequence of ones followed by
  33. * sequence of zeros. The number of ones specifies the size of the window in
  34. * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  35. * NOTE: A value of 0x0 specifies 64-KByte size.
  36. */
  37. unsigned int kw_winctrl_calcsize(unsigned int sizeval)
  38. {
  39. int i;
  40. unsigned int j = 0;
  41. u32 val = sizeval >> 1;
  42. for (i = 0; val >= 0x10000; i++) {
  43. j |= (1 << i);
  44. val = val >> 1;
  45. }
  46. return (0x0000ffff & j);
  47. }
  48. static struct mbus_win windows[] = {
  49. /* Window 0: PCIE MEM address space */
  50. { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
  51. KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
  52. /* Window 1: PCIE IO address space */
  53. { KW_DEFADR_PCI_IO, 1024 * 64,
  54. KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
  55. /* Window 2: NAND Flash address space */
  56. { KW_DEFADR_NANDF, 1024 * 1024 * 128,
  57. KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
  58. /* Window 3: SPI Flash address space */
  59. { KW_DEFADR_SPIF, 1024 * 1024 * 128,
  60. KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
  61. /* Window 4: BOOT Memory address space */
  62. { KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
  63. KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
  64. /* Window 5: Security SRAM address space */
  65. { KW_DEFADR_SASRAM, 1024 * 64,
  66. KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
  67. };
  68. /*
  69. * SYSRSTn Duration Counter Support
  70. *
  71. * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
  72. * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
  73. * The SYSRSTn duration counter is useful for implementing a manufacturer
  74. * or factory reset. Upon a long reset assertion that is greater than a
  75. * pre-configured environment variable value for sysrstdelay,
  76. * The counter value is stored in the SYSRSTn Length Counter Register
  77. * The counter is based on the 25-MHz reference clock (40ns)
  78. * It is a 29-bit counter, yielding a maximum counting duration of
  79. * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
  80. * it remains at this value until counter reset is triggered by setting
  81. * bit 31 of KW_REG_SYSRST_CNT
  82. */
  83. static void kw_sysrst_action(void)
  84. {
  85. int ret;
  86. char *s = env_get("sysrstcmd");
  87. if (!s) {
  88. debug("Error.. %s failed, check sysrstcmd\n",
  89. __FUNCTION__);
  90. return;
  91. }
  92. debug("Starting %s process...\n", __FUNCTION__);
  93. ret = run_command(s, 0);
  94. if (ret != 0)
  95. debug("Error.. %s failed\n", __FUNCTION__);
  96. else
  97. debug("%s process finished\n", __FUNCTION__);
  98. }
  99. static void kw_sysrst_check(void)
  100. {
  101. u32 sysrst_cnt, sysrst_dly;
  102. char *s;
  103. /*
  104. * no action if sysrstdelay environment variable is not defined
  105. */
  106. s = env_get("sysrstdelay");
  107. if (s == NULL)
  108. return;
  109. /* read sysrstdelay value */
  110. sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
  111. /* read SysRst Length counter register (bits 28:0) */
  112. sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
  113. debug("H/w Rst hold time: %d.%d secs\n",
  114. sysrst_cnt / SYSRST_CNT_1SEC_VAL,
  115. sysrst_cnt % SYSRST_CNT_1SEC_VAL);
  116. /* clear the counter for next valid read*/
  117. writel(1 << 31, KW_REG_SYSRST_CNT);
  118. /*
  119. * sysrst_action:
  120. * if H/w Reset key is pressed and hold for time
  121. * more than sysrst_dly in seconds
  122. */
  123. if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
  124. kw_sysrst_action();
  125. }
  126. #if defined(CONFIG_DISPLAY_CPUINFO)
  127. int print_cpuinfo(void)
  128. {
  129. char *rev = "??";
  130. u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
  131. u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
  132. if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
  133. printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
  134. return -1;
  135. }
  136. switch (revid) {
  137. case 0:
  138. if (devid == 0x6281)
  139. rev = "Z0";
  140. else if (devid == 0x6282)
  141. rev = "A0";
  142. break;
  143. case 1:
  144. rev = "A1";
  145. break;
  146. case 2:
  147. rev = "A0";
  148. break;
  149. case 3:
  150. rev = "A1";
  151. break;
  152. default:
  153. break;
  154. }
  155. printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
  156. return 0;
  157. }
  158. #endif /* CONFIG_DISPLAY_CPUINFO */
  159. #ifdef CONFIG_ARCH_CPU_INIT
  160. int arch_cpu_init(void)
  161. {
  162. u32 reg;
  163. struct kwcpu_registers *cpureg =
  164. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  165. /* Linux expects the internal registers to be at 0xf1000000 */
  166. writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
  167. /* Enable and invalidate L2 cache in write through mode */
  168. writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
  169. invalidate_l2_cache();
  170. #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
  171. /*
  172. * Configures the I/O voltage of the pads connected to Egigabit
  173. * Ethernet interface to 1.8V
  174. * By default it is set to 3.3V
  175. */
  176. reg = readl(KW_REG_MPP_OUT_DRV_REG);
  177. reg |= (1 << 7);
  178. writel(reg, KW_REG_MPP_OUT_DRV_REG);
  179. #endif
  180. #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
  181. /*
  182. * Set egiga port0/1 in normal functional mode
  183. * This is required becasue on kirkwood by default ports are in reset mode
  184. * OS egiga driver may not have provision to set them in normal mode
  185. * and if u-boot is build without network support, network may fail at OS level
  186. */
  187. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
  188. reg &= ~(1 << 4); /* Clear PortReset Bit */
  189. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
  190. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
  191. reg &= ~(1 << 4); /* Clear PortReset Bit */
  192. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
  193. #endif
  194. #ifdef CONFIG_KIRKWOOD_PCIE_INIT
  195. /*
  196. * Enable PCI Express Port0
  197. */
  198. reg = readl(&cpureg->ctrl_stat);
  199. reg |= (1 << 0); /* Set PEX0En Bit */
  200. writel(reg, &cpureg->ctrl_stat);
  201. #endif
  202. return 0;
  203. }
  204. #endif /* CONFIG_ARCH_CPU_INIT */
  205. /*
  206. * SOC specific misc init
  207. */
  208. #if defined(CONFIG_ARCH_MISC_INIT)
  209. int arch_misc_init(void)
  210. {
  211. volatile u32 temp;
  212. /*CPU streaming & write allocate */
  213. temp = readfr_extra_feature_reg();
  214. temp &= ~(1 << 28); /* disable wr alloc */
  215. writefr_extra_feature_reg(temp);
  216. temp = readfr_extra_feature_reg();
  217. temp &= ~(1 << 29); /* streaming disabled */
  218. writefr_extra_feature_reg(temp);
  219. /* L2Cache settings */
  220. temp = readfr_extra_feature_reg();
  221. /* Disable L2C pre fetch - Set bit 24 */
  222. temp |= (1 << 24);
  223. /* enable L2C - Set bit 22 */
  224. temp |= (1 << 22);
  225. writefr_extra_feature_reg(temp);
  226. /* Change reset vector to address 0x0 */
  227. temp = get_cr();
  228. set_cr(temp & ~CR_V);
  229. /* Configure mbus windows */
  230. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  231. /* checks and execute resset to factory event */
  232. kw_sysrst_check();
  233. return 0;
  234. }
  235. #endif /* CONFIG_ARCH_MISC_INIT */
  236. #ifdef CONFIG_MVGBE
  237. int cpu_eth_init(bd_t *bis)
  238. {
  239. mvgbe_initialize(bis);
  240. return 0;
  241. }
  242. #endif
  243. #ifdef CONFIG_MVEBU_MMC
  244. int board_mmc_init(bd_t *bis)
  245. {
  246. mvebu_mmc_init(bis);
  247. return 0;
  248. }
  249. #endif /* CONFIG_MVEBU_MMC */