j721e_init.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * J721E: SoC specific initialization
  4. *
  5. * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #include <asm/armv7_mpu.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sysfw-loader.h>
  15. #include "common.h"
  16. #include <asm/arch/sys_proto.h>
  17. #include <linux/soc/ti/ti_sci_protocol.h>
  18. #include <dm.h>
  19. #include <dm/uclass-internal.h>
  20. #include <dm/pinctrl.h>
  21. #include <mmc.h>
  22. #include <remoteproc.h>
  23. #ifdef CONFIG_SPL_BUILD
  24. #ifdef CONFIG_K3_LOAD_SYSFW
  25. #ifdef CONFIG_TI_SECURE_DEVICE
  26. struct fwl_data cbass_hc_cfg0_fwls[] = {
  27. { "PCIE0_CFG", 2560, 8 },
  28. { "PCIE1_CFG", 2561, 8 },
  29. { "USB3SS0_CORE", 2568, 4 },
  30. { "USB3SS1_CORE", 2570, 4 },
  31. { "EMMC8SS0_CFG", 2576, 4 },
  32. { "UFS_HCI0_CFG", 2580, 4 },
  33. { "SERDES0", 2584, 1 },
  34. { "SERDES1", 2585, 1 },
  35. }, cbass_hc0_fwls[] = {
  36. { "PCIE0_HP", 2528, 24 },
  37. { "PCIE0_LP", 2529, 24 },
  38. { "PCIE1_HP", 2530, 24 },
  39. { "PCIE1_LP", 2531, 24 },
  40. }, cbass_rc_cfg0_fwls[] = {
  41. { "EMMCSD4SS0_CFG", 2380, 4 },
  42. }, cbass_rc0_fwls[] = {
  43. { "GPMC0", 2310, 8 },
  44. }, infra_cbass0_fwls[] = {
  45. { "PLL_MMR0", 8, 26 },
  46. { "CTRL_MMR0", 9, 16 },
  47. }, mcu_cbass0_fwls[] = {
  48. { "MCU_R5FSS0_CORE0", 1024, 4 },
  49. { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  50. { "MCU_R5FSS0_CORE1", 1028, 4 },
  51. { "MCU_FSS0_CFG", 1032, 12 },
  52. { "MCU_FSS0_S1", 1033, 8 },
  53. { "MCU_FSS0_S0", 1036, 8 },
  54. { "MCU_PSROM49152X32", 1048, 1 },
  55. { "MCU_MSRAM128KX64", 1050, 8 },
  56. { "MCU_CTRL_MMR0", 1200, 8 },
  57. { "MCU_PLL_MMR0", 1201, 3 },
  58. { "MCU_CPSW0", 1220, 2 },
  59. }, wkup_cbass0_fwls[] = {
  60. { "WKUP_CTRL_MMR0", 131, 16 },
  61. };
  62. #endif
  63. #endif
  64. static void mmr_unlock(u32 base, u32 partition)
  65. {
  66. /* Translate the base address */
  67. phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  68. /* Unlock the requested partition if locked using two-step sequence */
  69. writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  70. writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  71. }
  72. static void ctrl_mmr_unlock(void)
  73. {
  74. /* Unlock all WKUP_CTRL_MMR0 module registers */
  75. mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  76. mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  77. mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  78. mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  79. mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  80. mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  81. mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  82. /* Unlock all MCU_CTRL_MMR0 module registers */
  83. mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  84. mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  85. mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  86. mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  87. mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  88. /* Unlock all CTRL_MMR0 module registers */
  89. mmr_unlock(CTRL_MMR0_BASE, 0);
  90. mmr_unlock(CTRL_MMR0_BASE, 1);
  91. mmr_unlock(CTRL_MMR0_BASE, 2);
  92. mmr_unlock(CTRL_MMR0_BASE, 3);
  93. mmr_unlock(CTRL_MMR0_BASE, 4);
  94. mmr_unlock(CTRL_MMR0_BASE, 5);
  95. mmr_unlock(CTRL_MMR0_BASE, 6);
  96. mmr_unlock(CTRL_MMR0_BASE, 7);
  97. }
  98. #if defined(CONFIG_K3_LOAD_SYSFW)
  99. void k3_mmc_stop_clock(void)
  100. {
  101. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  102. struct mmc *mmc = find_mmc_device(0);
  103. if (!mmc)
  104. return;
  105. mmc->saved_clock = mmc->clock;
  106. mmc_set_clock(mmc, 0, true);
  107. }
  108. }
  109. void k3_mmc_restart_clock(void)
  110. {
  111. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  112. struct mmc *mmc = find_mmc_device(0);
  113. if (!mmc)
  114. return;
  115. mmc_set_clock(mmc, mmc->saved_clock, false);
  116. }
  117. }
  118. #endif
  119. /*
  120. * This uninitialized global variable would normal end up in the .bss section,
  121. * but the .bss is cleared between writing and reading this variable, so move
  122. * it to the .data section.
  123. */
  124. u32 bootindex __attribute__((section(".data")));
  125. static void store_boot_index_from_rom(void)
  126. {
  127. bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  128. }
  129. void board_init_f(ulong dummy)
  130. {
  131. #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
  132. struct udevice *dev;
  133. int ret;
  134. #endif
  135. /*
  136. * Cannot delay this further as there is a chance that
  137. * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  138. */
  139. store_boot_index_from_rom();
  140. /* Make all control module registers accessible */
  141. ctrl_mmr_unlock();
  142. #ifdef CONFIG_CPU_V7R
  143. disable_linefill_optimization();
  144. setup_k3_mpu_regions();
  145. #endif
  146. /* Init DM early */
  147. spl_early_init();
  148. #ifdef CONFIG_K3_LOAD_SYSFW
  149. /*
  150. * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
  151. * regardless of the result of pinctrl. Do this without probing the
  152. * device, but instead by searching the device that would request the
  153. * given sequence number if probed. The UART will be used by the system
  154. * firmware (SYSFW) image for various purposes and SYSFW depends on us
  155. * to initialize its pin settings.
  156. */
  157. ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
  158. if (!ret)
  159. pinctrl_select_state(dev, "default");
  160. /*
  161. * Load, start up, and configure system controller firmware. Provide
  162. * the U-Boot console init function to the SYSFW post-PM configuration
  163. * callback hook, effectively switching on (or over) the console
  164. * output.
  165. */
  166. k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
  167. /* Prepare console output */
  168. preloader_console_init();
  169. /* Disable ROM configured firewalls right after loading sysfw */
  170. #ifdef CONFIG_TI_SECURE_DEVICE
  171. remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
  172. remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
  173. remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
  174. remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
  175. remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
  176. remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
  177. remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
  178. #endif
  179. #else
  180. /* Prepare console output */
  181. preloader_console_init();
  182. #endif
  183. /* Output System Firmware version info */
  184. k3_sysfw_print_ver();
  185. /* Perform EEPROM-based board detection */
  186. do_board_detect();
  187. #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
  188. ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
  189. &dev);
  190. if (ret)
  191. printf("AVS init failed: %d\n", ret);
  192. #endif
  193. #if defined(CONFIG_K3_J721E_DDRSS)
  194. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  195. if (ret)
  196. panic("DRAM init failed: %d\n", ret);
  197. #endif
  198. }
  199. u32 spl_mmc_boot_mode(const u32 boot_device)
  200. {
  201. switch (boot_device) {
  202. case BOOT_DEVICE_MMC1:
  203. return MMCSD_MODE_EMMCBOOT;
  204. case BOOT_DEVICE_MMC2:
  205. return MMCSD_MODE_FS;
  206. default:
  207. return MMCSD_MODE_RAW;
  208. }
  209. }
  210. static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
  211. {
  212. u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
  213. WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
  214. bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
  215. BOOT_MODE_B_SHIFT;
  216. if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
  217. bootmode = BOOT_DEVICE_SPI;
  218. if (bootmode == BOOT_DEVICE_MMC2) {
  219. u32 port = (main_devstat &
  220. MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
  221. MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
  222. if (port == 0x0)
  223. bootmode = BOOT_DEVICE_MMC1;
  224. }
  225. return bootmode;
  226. }
  227. u32 spl_boot_device(void)
  228. {
  229. u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
  230. u32 main_devstat;
  231. if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
  232. printf("ERROR: MCU only boot is not yet supported\n");
  233. return BOOT_DEVICE_RAM;
  234. }
  235. /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
  236. main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  237. /* ToDo: Add support for backup boot media */
  238. return __get_primary_bootmedia(main_devstat, wkup_devstat);
  239. }
  240. #endif
  241. #ifdef CONFIG_SYS_K3_SPL_ATF
  242. #define J721E_DEV_MCU_RTI0 262
  243. #define J721E_DEV_MCU_RTI1 263
  244. #define J721E_DEV_MCU_ARMSS0_CPU0 250
  245. #define J721E_DEV_MCU_ARMSS0_CPU1 251
  246. void release_resources_for_core_shutdown(void)
  247. {
  248. struct ti_sci_handle *ti_sci;
  249. struct ti_sci_dev_ops *dev_ops;
  250. struct ti_sci_proc_ops *proc_ops;
  251. int ret;
  252. u32 i;
  253. const u32 put_device_ids[] = {
  254. J721E_DEV_MCU_RTI0,
  255. J721E_DEV_MCU_RTI1,
  256. };
  257. ti_sci = get_ti_sci_handle();
  258. dev_ops = &ti_sci->ops.dev_ops;
  259. proc_ops = &ti_sci->ops.proc_ops;
  260. /* Iterate through list of devices to put (shutdown) */
  261. for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
  262. u32 id = put_device_ids[i];
  263. ret = dev_ops->put_device(ti_sci, id);
  264. if (ret)
  265. panic("Failed to put device %u (%d)\n", id, ret);
  266. }
  267. const u32 put_core_ids[] = {
  268. J721E_DEV_MCU_ARMSS0_CPU1,
  269. J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
  270. };
  271. /* Iterate through list of cores to put (shutdown) */
  272. for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
  273. u32 id = put_core_ids[i];
  274. /*
  275. * Queue up the core shutdown request. Note that this call
  276. * needs to be followed up by an actual invocation of an WFE
  277. * or WFI CPU instruction.
  278. */
  279. ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
  280. if (ret)
  281. panic("Failed sending core %u shutdown message (%d)\n",
  282. id, ret);
  283. }
  284. }
  285. #endif
  286. #ifdef CONFIG_SYS_K3_SPL_ATF
  287. void start_non_linux_remote_cores(void)
  288. {
  289. int size = 0, ret;
  290. u32 loadaddr = 0;
  291. size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
  292. &loadaddr);
  293. if (size <= 0)
  294. goto err_load;
  295. /* assuming remoteproc 2 is aliased for the needed remotecore */
  296. ret = rproc_load(2, loadaddr, size);
  297. if (ret) {
  298. printf("Firmware failed to start on rproc (%d)\n", ret);
  299. goto err_load;
  300. }
  301. ret = rproc_start(2);
  302. if (ret) {
  303. printf("Firmware init failed on rproc (%d)\n", ret);
  304. goto err_load;
  305. }
  306. printf("Remoteproc 2 started successfully\n");
  307. return;
  308. err_load:
  309. rproc_reset(2);
  310. }
  311. #endif