am6_init.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * AM6: SoC specific initialization
  4. *
  5. * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <spl.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/sysfw-loader.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include "common.h"
  16. #include <dm.h>
  17. #include <dm/uclass-internal.h>
  18. #include <dm/pinctrl.h>
  19. #include <linux/soc/ti/ti_sci_protocol.h>
  20. #include <mmc.h>
  21. #ifdef CONFIG_SPL_BUILD
  22. #ifdef CONFIG_K3_LOAD_SYSFW
  23. #ifdef CONFIG_TI_SECURE_DEVICE
  24. struct fwl_data main_cbass_fwls[] = {
  25. { "MMCSD1_CFG", 2057, 1 },
  26. { "MMCSD0_CFG", 2058, 1 },
  27. { "USB3SS0_SLV0", 2176, 2 },
  28. { "PCIE0_SLV", 2336, 8 },
  29. { "PCIE1_SLV", 2337, 8 },
  30. { "PCIE0_CFG", 2688, 1 },
  31. { "PCIE1_CFG", 2689, 1 },
  32. }, mcu_cbass_fwls[] = {
  33. { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  34. { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  35. { "MCU_FSS0_S1", 1033, 8 },
  36. { "MCU_FSS0_S0", 1036, 8 },
  37. { "MCU_CPSW0", 1220, 1 },
  38. };
  39. #endif
  40. #endif
  41. static void mmr_unlock(u32 base, u32 partition)
  42. {
  43. /* Translate the base address */
  44. phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  45. /* Unlock the requested partition if locked using two-step sequence */
  46. writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  47. writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  48. }
  49. static void ctrl_mmr_unlock(void)
  50. {
  51. /* Unlock all WKUP_CTRL_MMR0 module registers */
  52. mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  53. mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  54. mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  55. mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  56. mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  57. mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  58. /* Unlock all MCU_CTRL_MMR0 module registers */
  59. mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  60. mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  61. mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  62. mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  63. /* Unlock all CTRL_MMR0 module registers */
  64. mmr_unlock(CTRL_MMR0_BASE, 0);
  65. mmr_unlock(CTRL_MMR0_BASE, 1);
  66. mmr_unlock(CTRL_MMR0_BASE, 2);
  67. mmr_unlock(CTRL_MMR0_BASE, 3);
  68. mmr_unlock(CTRL_MMR0_BASE, 6);
  69. mmr_unlock(CTRL_MMR0_BASE, 7);
  70. }
  71. /*
  72. * This uninitialized global variable would normal end up in the .bss section,
  73. * but the .bss is cleared between writing and reading this variable, so move
  74. * it to the .data section.
  75. */
  76. u32 bootindex __attribute__((section(".data")));
  77. static void store_boot_index_from_rom(void)
  78. {
  79. bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  80. }
  81. #if defined(CONFIG_K3_LOAD_SYSFW)
  82. void k3_mmc_stop_clock(void)
  83. {
  84. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  85. struct mmc *mmc = find_mmc_device(0);
  86. if (!mmc)
  87. return;
  88. mmc->saved_clock = mmc->clock;
  89. mmc_set_clock(mmc, 0, true);
  90. }
  91. }
  92. void k3_mmc_restart_clock(void)
  93. {
  94. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  95. struct mmc *mmc = find_mmc_device(0);
  96. if (!mmc)
  97. return;
  98. mmc_set_clock(mmc, mmc->saved_clock, false);
  99. }
  100. }
  101. #endif
  102. void board_init_f(ulong dummy)
  103. {
  104. #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  105. struct udevice *dev;
  106. int ret;
  107. #endif
  108. /*
  109. * Cannot delay this further as there is a chance that
  110. * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  111. */
  112. store_boot_index_from_rom();
  113. /* Make all control module registers accessible */
  114. ctrl_mmr_unlock();
  115. #ifdef CONFIG_CPU_V7R
  116. disable_linefill_optimization();
  117. setup_k3_mpu_regions();
  118. #endif
  119. /* Init DM early in-order to invoke system controller */
  120. spl_early_init();
  121. #ifdef CONFIG_K3_EARLY_CONS
  122. /*
  123. * Allow establishing an early console as required for example when
  124. * doing a UART-based boot. Note that this console may not "survive"
  125. * through a SYSFW PM-init step and will need a re-init in some way
  126. * due to changing module clock frequencies.
  127. */
  128. early_console_init();
  129. #endif
  130. #ifdef CONFIG_K3_LOAD_SYSFW
  131. /*
  132. * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  133. * regardless of the result of pinctrl. Do this without probing the
  134. * device, but instead by searching the device that would request the
  135. * given sequence number if probed. The UART will be used by the system
  136. * firmware (SYSFW) image for various purposes and SYSFW depends on us
  137. * to initialize its pin settings.
  138. */
  139. ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
  140. if (!ret)
  141. pinctrl_select_state(dev, "default");
  142. /*
  143. * Load, start up, and configure system controller firmware while
  144. * also populating the SYSFW post-PM configuration callback hook.
  145. */
  146. k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
  147. /* Prepare console output */
  148. preloader_console_init();
  149. /* Disable ROM configured firewalls right after loading sysfw */
  150. #ifdef CONFIG_TI_SECURE_DEVICE
  151. remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
  152. remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
  153. #endif
  154. #else
  155. /* Prepare console output */
  156. preloader_console_init();
  157. #endif
  158. /* Output System Firmware version info */
  159. k3_sysfw_print_ver();
  160. /* Perform EEPROM-based board detection */
  161. do_board_detect();
  162. #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
  163. ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
  164. &dev);
  165. if (ret)
  166. printf("AVS init failed: %d\n", ret);
  167. #endif
  168. #ifdef CONFIG_K3_AM654_DDRSS
  169. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  170. if (ret)
  171. panic("DRAM init failed: %d\n", ret);
  172. #endif
  173. }
  174. u32 spl_mmc_boot_mode(const u32 boot_device)
  175. {
  176. #if defined(CONFIG_SUPPORT_EMMC_BOOT)
  177. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  178. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  179. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  180. /* eMMC boot0 mode is only supported for primary boot */
  181. if (bootindex == K3_PRIMARY_BOOTMODE &&
  182. bootmode == BOOT_DEVICE_MMC1)
  183. return MMCSD_MODE_EMMCBOOT;
  184. #endif
  185. /* Everything else use filesystem if available */
  186. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  187. return MMCSD_MODE_FS;
  188. #else
  189. return MMCSD_MODE_RAW;
  190. #endif
  191. }
  192. static u32 __get_backup_bootmedia(u32 devstat)
  193. {
  194. u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
  195. CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
  196. switch (bkup_boot) {
  197. case BACKUP_BOOT_DEVICE_USB:
  198. return BOOT_DEVICE_USB;
  199. case BACKUP_BOOT_DEVICE_UART:
  200. return BOOT_DEVICE_UART;
  201. case BACKUP_BOOT_DEVICE_ETHERNET:
  202. return BOOT_DEVICE_ETHERNET;
  203. case BACKUP_BOOT_DEVICE_MMC2:
  204. {
  205. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
  206. CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
  207. if (port == 0x0)
  208. return BOOT_DEVICE_MMC1;
  209. return BOOT_DEVICE_MMC2;
  210. }
  211. case BACKUP_BOOT_DEVICE_SPI:
  212. return BOOT_DEVICE_SPI;
  213. case BACKUP_BOOT_DEVICE_HYPERFLASH:
  214. return BOOT_DEVICE_HYPERFLASH;
  215. case BACKUP_BOOT_DEVICE_I2C:
  216. return BOOT_DEVICE_I2C;
  217. };
  218. return BOOT_DEVICE_RAM;
  219. }
  220. static u32 __get_primary_bootmedia(u32 devstat)
  221. {
  222. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  223. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  224. if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
  225. bootmode = BOOT_DEVICE_SPI;
  226. if (bootmode == BOOT_DEVICE_MMC2) {
  227. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
  228. CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
  229. if (port == 0x0)
  230. bootmode = BOOT_DEVICE_MMC1;
  231. } else if (bootmode == BOOT_DEVICE_MMC1) {
  232. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
  233. CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
  234. if (port == 0x1)
  235. bootmode = BOOT_DEVICE_MMC2;
  236. }
  237. return bootmode;
  238. }
  239. u32 spl_boot_device(void)
  240. {
  241. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  242. if (bootindex == K3_PRIMARY_BOOTMODE)
  243. return __get_primary_bootmedia(devstat);
  244. else
  245. return __get_backup_bootmedia(devstat);
  246. }
  247. #endif
  248. #ifdef CONFIG_SYS_K3_SPL_ATF
  249. #define AM6_DEV_MCU_RTI0 134
  250. #define AM6_DEV_MCU_RTI1 135
  251. #define AM6_DEV_MCU_ARMSS0_CPU0 159
  252. #define AM6_DEV_MCU_ARMSS0_CPU1 245
  253. void release_resources_for_core_shutdown(void)
  254. {
  255. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  256. struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
  257. struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
  258. int ret;
  259. u32 i;
  260. const u32 put_device_ids[] = {
  261. AM6_DEV_MCU_RTI0,
  262. AM6_DEV_MCU_RTI1,
  263. };
  264. /* Iterate through list of devices to put (shutdown) */
  265. for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
  266. u32 id = put_device_ids[i];
  267. ret = dev_ops->put_device(ti_sci, id);
  268. if (ret)
  269. panic("Failed to put device %u (%d)\n", id, ret);
  270. }
  271. const u32 put_core_ids[] = {
  272. AM6_DEV_MCU_ARMSS0_CPU1,
  273. AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
  274. };
  275. /* Iterate through list of cores to put (shutdown) */
  276. for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
  277. u32 id = put_core_ids[i];
  278. /*
  279. * Queue up the core shutdown request. Note that this call
  280. * needs to be followed up by an actual invocation of an WFE
  281. * or WFI CPU instruction.
  282. */
  283. ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
  284. if (ret)
  285. panic("Failed sending core %u shutdown message (%d)\n",
  286. id, ret);
  287. }
  288. }
  289. #endif