spl_boot.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <init.h>
  8. #include <asm/cache.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/clk.h>
  11. #include <asm/arch/dmc.h>
  12. #include <asm/arch/periph.h>
  13. #include <asm/arch/pinmux.h>
  14. #include <asm/arch/power.h>
  15. #include <asm/arch/spl.h>
  16. #include <asm/arch/spi.h>
  17. #include "common_setup.h"
  18. #include "clock_init.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* Index into irom ptr table */
  21. enum index {
  22. MMC_INDEX,
  23. EMMC44_INDEX,
  24. EMMC44_END_INDEX,
  25. SPI_INDEX,
  26. USB_INDEX,
  27. };
  28. /* IROM Function Pointers Table */
  29. u32 irom_ptr_table[] = {
  30. [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
  31. [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
  32. [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
  33. -EMMC4.4 end boot operation */
  34. [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
  35. [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
  36. };
  37. void *get_irom_func(int index)
  38. {
  39. return (void *)*(u32 *)irom_ptr_table[index];
  40. }
  41. #ifdef CONFIG_USB_BOOTING
  42. /*
  43. * Set/clear program flow prediction and return the previous state.
  44. */
  45. static int config_branch_prediction(int set_cr_z)
  46. {
  47. unsigned int cr;
  48. /* System Control Register: 11th bit Z Branch prediction enable */
  49. cr = get_cr();
  50. set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
  51. return cr & CR_Z;
  52. }
  53. #endif
  54. #ifdef CONFIG_SPI_BOOTING
  55. static void spi_rx_tx(struct exynos_spi *regs, int todo,
  56. void *dinp, void const *doutp, int i)
  57. {
  58. uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
  59. int rx_lvl, tx_lvl;
  60. uint out_bytes, in_bytes;
  61. out_bytes = todo;
  62. in_bytes = todo;
  63. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  64. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  65. writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  66. while (in_bytes) {
  67. uint32_t spi_sts;
  68. int temp;
  69. spi_sts = readl(&regs->spi_sts);
  70. rx_lvl = ((spi_sts >> 15) & 0x7f);
  71. tx_lvl = ((spi_sts >> 6) & 0x7f);
  72. while (tx_lvl < 32 && out_bytes) {
  73. temp = 0xffffffff;
  74. writel(temp, &regs->tx_data);
  75. out_bytes -= 4;
  76. tx_lvl += 4;
  77. }
  78. while (rx_lvl >= 4 && in_bytes) {
  79. temp = readl(&regs->rx_data);
  80. if (rxp)
  81. *rxp++ = temp;
  82. in_bytes -= 4;
  83. rx_lvl -= 4;
  84. }
  85. }
  86. }
  87. /*
  88. * Copy uboot from spi flash to RAM
  89. *
  90. * @parma uboot_size size of u-boot to copy
  91. * @param uboot_addr address in u-boot to copy
  92. */
  93. static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
  94. {
  95. int upto, todo;
  96. int i, timeout = 100;
  97. struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
  98. set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
  99. /* set the spi1 GPIO */
  100. exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
  101. /* set pktcnt and enable it */
  102. writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  103. /* set FB_CLK_SEL */
  104. writel(SPI_FB_DELAY_180, &regs->fb_clk);
  105. /* set CH_WIDTH and BUS_WIDTH as word */
  106. setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  107. SPI_MODE_BUS_WIDTH_WORD);
  108. clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
  109. /* clear rx and tx channel if set priveously */
  110. clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  111. setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
  112. SPI_RX_BYTE_SWAP |
  113. SPI_RX_HWORD_SWAP);
  114. /* do a soft reset */
  115. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  116. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  117. /* now set rx and tx channel ON */
  118. setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
  119. clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
  120. /* Send read instruction (0x3h) followed by a 24 bit addr */
  121. writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
  122. /* waiting for TX done */
  123. while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
  124. if (!timeout) {
  125. debug("SPI TIMEOUT\n");
  126. break;
  127. }
  128. timeout--;
  129. }
  130. for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
  131. todo = min(uboot_size - upto, (unsigned int)(1 << 15));
  132. spi_rx_tx(regs, todo, (void *)(uboot_addr),
  133. (void *)(SPI_FLASH_UBOOT_POS), i);
  134. }
  135. setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
  136. /*
  137. * Let put controller mode to BYTE as
  138. * SPI driver does not support WORD mode yet
  139. */
  140. clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  141. SPI_MODE_BUS_WIDTH_WORD);
  142. writel(0, &regs->swap_cfg);
  143. /*
  144. * Flush spi tx, rx fifos and reset the SPI controller
  145. * and clear rx/tx channel
  146. */
  147. clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  148. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  149. clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  150. }
  151. #endif
  152. /*
  153. * Copy U-Boot from mmc to RAM:
  154. * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
  155. * Pointer to API (Data transfer from mmc to ram)
  156. */
  157. void copy_uboot_to_ram(void)
  158. {
  159. unsigned int bootmode = BOOT_MODE_OM;
  160. u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
  161. u32 offset = 0, size = 0;
  162. #ifdef CONFIG_SPI_BOOTING
  163. struct spl_machine_param *param = spl_get_machine_params();
  164. #endif
  165. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  166. u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
  167. void (*end_bootop_from_emmc)(void);
  168. #endif
  169. #ifdef CONFIG_USB_BOOTING
  170. int is_cr_z_set;
  171. unsigned int sec_boot_check;
  172. /*
  173. * Note that older hardware (before Exynos5800) does not expect any
  174. * arguments, but it does not hurt to pass them, so a common function
  175. * prototype is used.
  176. */
  177. u32 (*usb_copy)(u32 num_of_block, u32 *dst);
  178. /* Read iRAM location to check for secondary USB boot mode */
  179. sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
  180. if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
  181. bootmode = BOOT_MODE_USB;
  182. #endif
  183. if (bootmode == BOOT_MODE_OM)
  184. bootmode = get_boot_mode();
  185. switch (bootmode) {
  186. #ifdef CONFIG_SPI_BOOTING
  187. case BOOT_MODE_SERIAL:
  188. /* Customised function to copy u-boot from SF */
  189. exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
  190. break;
  191. #endif
  192. case BOOT_MODE_SD:
  193. offset = BL2_START_OFFSET;
  194. size = BL2_SIZE_BLOC_COUNT;
  195. copy_bl2 = get_irom_func(MMC_INDEX);
  196. break;
  197. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  198. case BOOT_MODE_EMMC:
  199. /* Set the FSYS1 clock divisor value for EMMC boot */
  200. emmc_boot_clk_div_set();
  201. copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
  202. end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
  203. copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
  204. end_bootop_from_emmc();
  205. break;
  206. #endif
  207. #ifdef CONFIG_USB_BOOTING
  208. case BOOT_MODE_USB:
  209. /*
  210. * iROM needs program flow prediction to be disabled
  211. * before copy from USB device to RAM
  212. */
  213. is_cr_z_set = config_branch_prediction(0);
  214. usb_copy = get_irom_func(USB_INDEX);
  215. usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
  216. config_branch_prediction(is_cr_z_set);
  217. break;
  218. #endif
  219. default:
  220. break;
  221. }
  222. if (copy_bl2)
  223. copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
  224. }
  225. void memzero(void *s, size_t n)
  226. {
  227. char *ptr = s;
  228. size_t i;
  229. for (i = 0; i < n; i++)
  230. *ptr++ = '\0';
  231. }
  232. /**
  233. * Set up the U-Boot global_data pointer
  234. *
  235. * This sets the address of the global data, and sets up basic values.
  236. *
  237. * @param gdp Value to give to gd
  238. */
  239. static void setup_global_data(gd_t *gdp)
  240. {
  241. gd = gdp;
  242. memzero((void *)gd, sizeof(gd_t));
  243. gd->flags |= GD_FLG_RELOC;
  244. gd->baudrate = CONFIG_BAUDRATE;
  245. gd->have_console = 1;
  246. }
  247. void board_init_f(unsigned long bootflag)
  248. {
  249. __aligned(8) gd_t local_gd;
  250. __attribute__((noreturn)) void (*uboot)(void);
  251. setup_global_data(&local_gd);
  252. if (do_lowlevel_init())
  253. power_exit_wakeup();
  254. copy_uboot_to_ram();
  255. /* Jump to U-Boot image */
  256. uboot = (void *)CONFIG_SYS_TEXT_BASE;
  257. (*uboot)();
  258. /* Never returns Here */
  259. }
  260. /* Place Holders */
  261. void board_init_r(gd_t *id, ulong dest_addr)
  262. {
  263. /* Function attribute is no-return */
  264. /* This Function never executes */
  265. while (1)
  266. ;
  267. }