lowlevel_init.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. /*
  2. * Lowlevel setup for EXYNOS5 based board
  3. *
  4. * Copyright (C) 2013 Samsung Electronics
  5. * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <config.h>
  27. #include <debug_uart.h>
  28. #include <asm/system.h>
  29. #include <init.h>
  30. #include <asm/arch/cpu.h>
  31. #include <asm/arch/dmc.h>
  32. #include <asm/arch/power.h>
  33. #include <asm/arch/tzpc.h>
  34. #include <asm/arch/periph.h>
  35. #include <asm/arch/pinmux.h>
  36. #include <asm/arch/system.h>
  37. #include <asm/armv7.h>
  38. #include "common_setup.h"
  39. #include "exynos5_setup.h"
  40. /* These are the things we can do during low-level init */
  41. enum {
  42. DO_WAKEUP = 1 << 0,
  43. DO_CLOCKS = 1 << 1,
  44. DO_MEM_RESET = 1 << 2,
  45. DO_UART = 1 << 3,
  46. DO_POWER = 1 << 4,
  47. };
  48. #ifdef CONFIG_EXYNOS5420
  49. /*
  50. * Power up secondary CPUs.
  51. */
  52. static void secondary_cpu_start(void)
  53. {
  54. v7_enable_smp(EXYNOS5420_INFORM_BASE);
  55. svc32_mode_en();
  56. branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
  57. }
  58. /*
  59. * This is the entry point of hotplug-in and
  60. * cluster switching.
  61. */
  62. static void low_power_start(void)
  63. {
  64. uint32_t val, reg_val;
  65. reg_val = readl(EXYNOS5420_SPARE_BASE);
  66. if (reg_val != CPU_RST_FLAG_VAL) {
  67. writel(0x0, CONFIG_LOWPOWER_FLAG);
  68. branch_bx(0x0);
  69. }
  70. reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
  71. if (reg_val != (uint32_t)&low_power_start) {
  72. /* Store jump address as low_power_start if not present */
  73. writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
  74. dsb();
  75. sev();
  76. }
  77. /* Set the CPU to SVC32 mode */
  78. svc32_mode_en();
  79. #ifndef CONFIG_SYS_L2CACHE_OFF
  80. /* Read MIDR for Primary Part Number */
  81. mrc_midr(val);
  82. val = (val >> 4);
  83. val &= 0xf;
  84. if (val == 0xf) {
  85. configure_l2_ctlr();
  86. configure_l2_actlr();
  87. v7_enable_l2_hazard_detect();
  88. }
  89. #endif
  90. /* Invalidate L1 & TLB */
  91. val = 0x0;
  92. mcr_tlb(val);
  93. mcr_icache(val);
  94. /* Disable MMU stuff and caches */
  95. mrc_sctlr(val);
  96. val &= ~((0x2 << 12) | 0x7);
  97. val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
  98. mcr_sctlr(val);
  99. /* CPU state is hotplug or reset */
  100. secondary_cpu_start();
  101. /* Core should not enter into WFI here */
  102. wfi();
  103. }
  104. /*
  105. * Pointer to this function is stored in iRam which is used
  106. * for jump and power down of a specific core.
  107. */
  108. static void power_down_core(void)
  109. {
  110. uint32_t tmp, core_id, core_config;
  111. /* Get the unique core id */
  112. /*
  113. * Multiprocessor Affinity Register
  114. * [11:8] Cluster ID
  115. * [1:0] CPU ID
  116. */
  117. mrc_mpafr(core_id);
  118. tmp = core_id & 0x3;
  119. core_id = (core_id >> 6) & ~3;
  120. core_id |= tmp;
  121. core_id &= 0x3f;
  122. /* Set the status of the core to low */
  123. core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
  124. core_config += EXYNOS5420_CPU_CONFIG_BASE;
  125. writel(0x0, core_config);
  126. /* Core enter WFI */
  127. wfi();
  128. }
  129. /*
  130. * Configurations for secondary cores are inapt at this stage.
  131. * Reconfigure secondary cores. Shutdown and change the status
  132. * of all cores except the primary core.
  133. */
  134. static void secondary_cores_configure(void)
  135. {
  136. /* Clear secondary boot iRAM base */
  137. writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
  138. /* set lowpower flag and address */
  139. writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
  140. writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
  141. writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
  142. /* Store jump address for power down */
  143. writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
  144. /* Need all core power down check */
  145. dsb();
  146. sev();
  147. }
  148. extern void relocate_wait_code(void);
  149. #endif
  150. int do_lowlevel_init(void)
  151. {
  152. uint32_t reset_status;
  153. int actions = 0;
  154. arch_cpu_init();
  155. #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
  156. /*
  157. * Init L2 cache parameters here for use by boot and resume
  158. *
  159. * These are here instead of in v7_outer_cache_enable() so that the
  160. * L2 cache settings get properly set even at resume time or if we're
  161. * running U-Boot with the cache off. The kernel still needs us to
  162. * set these for it.
  163. */
  164. configure_l2_ctlr();
  165. configure_l2_actlr();
  166. dsb();
  167. isb();
  168. relocate_wait_code();
  169. /* Reconfigure secondary cores */
  170. secondary_cores_configure();
  171. #endif
  172. reset_status = get_reset_status();
  173. switch (reset_status) {
  174. case S5P_CHECK_SLEEP:
  175. actions = DO_CLOCKS | DO_WAKEUP;
  176. break;
  177. case S5P_CHECK_DIDLE:
  178. case S5P_CHECK_LPA:
  179. actions = DO_WAKEUP;
  180. break;
  181. default:
  182. /* This is a normal boot (not a wake from sleep) */
  183. actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
  184. }
  185. if (actions & DO_POWER)
  186. set_ps_hold_ctrl();
  187. if (actions & DO_CLOCKS) {
  188. system_clock_init();
  189. #ifdef CONFIG_DEBUG_UART
  190. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
  191. !defined(CONFIG_SPL_BUILD)
  192. exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
  193. debug_uart_init();
  194. #endif
  195. #endif
  196. mem_ctrl_init(actions & DO_MEM_RESET);
  197. tzpc_init();
  198. }
  199. return actions & DO_WAKEUP;
  200. }