da850_lowlevel.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SoC-specific lowlevel code for DA850
  4. *
  5. * Copyright (C) 2011
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <nand.h>
  11. #include <ns16550.h>
  12. #include <post.h>
  13. #include <asm/arch/da850_lowlevel.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/davinci_misc.h>
  16. #include <asm/arch/ddr2_defs.h>
  17. #include <asm/ti-common/davinci_nand.h>
  18. #include <asm/arch/pll_defs.h>
  19. void davinci_enable_uart0(void)
  20. {
  21. lpsc_on(DAVINCI_LPSC_UART0);
  22. /* Bringup UART0 out of reset */
  23. REG(UART0_PWREMU_MGMT) = 0x00006001;
  24. }
  25. #if defined(CONFIG_SYS_DA850_PLL_INIT)
  26. static void da850_waitloop(unsigned long loopcnt)
  27. {
  28. unsigned long i;
  29. for (i = 0; i < loopcnt; i++)
  30. asm(" NOP");
  31. }
  32. static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
  33. {
  34. if (reg == davinci_pllc0_regs)
  35. /* Unlock PLL registers. */
  36. clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
  37. /*
  38. * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
  39. * through MMR
  40. */
  41. clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
  42. /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
  43. clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
  44. /* Set PLLEN=0 => PLL BYPASS MODE */
  45. clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
  46. da850_waitloop(150);
  47. if (reg == davinci_pllc0_regs) {
  48. /*
  49. * Select the Clock Mode bit 8 as External Clock or On Chip
  50. * Oscilator
  51. */
  52. dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
  53. setbits_le32(&reg->pllctl,
  54. (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
  55. }
  56. /* Clear PLLRST bit to reset the PLL */
  57. clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
  58. /* Disable the PLL output */
  59. setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  60. /* PLL initialization sequence */
  61. /*
  62. * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
  63. * power down bit
  64. */
  65. clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
  66. /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
  67. clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  68. #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
  69. /* program the prediv */
  70. if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
  71. writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
  72. &reg->prediv);
  73. #endif
  74. /* Program the required multiplier value in PLLM */
  75. writel(pllmult, &reg->pllm);
  76. /* program the postdiv */
  77. if (reg == davinci_pllc0_regs)
  78. writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
  79. &reg->postdiv);
  80. else
  81. writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
  82. &reg->postdiv);
  83. /*
  84. * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
  85. * no GO operation is currently in progress
  86. */
  87. while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
  88. ;
  89. if (reg == davinci_pllc0_regs) {
  90. writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
  91. writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
  92. writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
  93. writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
  94. writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
  95. writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
  96. writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
  97. } else {
  98. writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
  99. writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
  100. writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
  101. }
  102. /*
  103. * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
  104. * transition.
  105. */
  106. setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
  107. /*
  108. * Wait for the GOSTAT bit in PLLSTAT to clear to 0
  109. * (completion of phase alignment).
  110. */
  111. while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
  112. ;
  113. /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
  114. da850_waitloop(200);
  115. /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
  116. setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
  117. /* Wait for PLL to lock. See PLL spec for PLL lock time */
  118. da850_waitloop(2400);
  119. /*
  120. * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
  121. * mode
  122. */
  123. setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
  124. /*
  125. * clear EMIFA and EMIFB clock source settings, let them
  126. * run off SYSCLK
  127. */
  128. if (reg == davinci_pllc0_regs)
  129. dv_maskbits(&davinci_syscfg_regs->cfgchip3,
  130. ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
  131. return 0;
  132. }
  133. #endif /* CONFIG_SYS_DA850_PLL_INIT */
  134. #if defined(CONFIG_SYS_DA850_DDR_INIT)
  135. static int da850_ddr_setup(void)
  136. {
  137. unsigned long tmp;
  138. /* Enable the Clock to DDR2/mDDR */
  139. lpsc_on(DAVINCI_LPSC_DDR_EMIF);
  140. tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
  141. if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
  142. /* Begin VTP Calibration */
  143. clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
  144. clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
  145. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
  146. clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
  147. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
  148. /* Polling READY bit to see when VTP calibration is done */
  149. tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
  150. while ((tmp & VTP_READY) != VTP_READY)
  151. tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
  152. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
  153. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
  154. }
  155. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
  156. writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
  157. if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
  158. /* DDR2 */
  159. clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
  160. (1 << DDR_SLEW_DDR_PDENA_BIT) |
  161. (1 << DDR_SLEW_CMOSEN_BIT));
  162. } else {
  163. /* MOBILE DDR */
  164. setbits_le32(&davinci_syscfg1_regs->ddr_slew,
  165. (1 << DDR_SLEW_DDR_PDENA_BIT) |
  166. (1 << DDR_SLEW_CMOSEN_BIT));
  167. }
  168. /*
  169. * SDRAM Configuration Register (SDCR):
  170. * First set the BOOTUNLOCK bit to make configuration bits
  171. * writeable.
  172. */
  173. setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
  174. /*
  175. * Write the new value of these bits and clear BOOTUNLOCK.
  176. * At the same time, set the TIMUNLOCK bit to allow changing
  177. * the timing registers
  178. */
  179. tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
  180. tmp &= ~DV_DDR_BOOTUNLOCK;
  181. tmp |= DV_DDR_TIMUNLOCK;
  182. writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
  183. /* write memory configuration and timing */
  184. if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
  185. /* MOBILE DDR only*/
  186. writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
  187. &dv_ddr2_regs_ctrl->sdbcr2);
  188. }
  189. writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
  190. writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
  191. /* clear the TIMUNLOCK bit and write the value of the CL field */
  192. tmp &= ~DV_DDR_TIMUNLOCK;
  193. writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
  194. /*
  195. * LPMODEN and MCLKSTOPEN must be set!
  196. * Without this bits set, PSC don;t switch states !!
  197. */
  198. writel(CONFIG_SYS_DA850_DDR2_SDRCR |
  199. (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
  200. (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
  201. &dv_ddr2_regs_ctrl->sdrcr);
  202. /* SyncReset the Clock to EMIF3A SDRAM */
  203. lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
  204. /* Enable the Clock to EMIF3A SDRAM */
  205. lpsc_on(DAVINCI_LPSC_DDR_EMIF);
  206. /* disable self refresh */
  207. clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
  208. DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
  209. writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
  210. return 0;
  211. }
  212. #endif /* CONFIG_SYS_DA850_DDR_INIT */
  213. __attribute__((weak))
  214. void board_gpio_init(void)
  215. {
  216. return;
  217. }
  218. int arch_cpu_init(void)
  219. {
  220. /* Unlock kick registers */
  221. writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
  222. writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
  223. dv_maskbits(&davinci_syscfg_regs->suspsrc,
  224. CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
  225. /* configure pinmux settings */
  226. if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
  227. return 1;
  228. #if defined(CONFIG_SYS_DA850_PLL_INIT)
  229. /* PLL setup */
  230. da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
  231. da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
  232. #endif
  233. /* setup CSn config */
  234. #if defined(CONFIG_SYS_DA850_CS2CFG)
  235. writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
  236. #endif
  237. #if defined(CONFIG_SYS_DA850_CS3CFG)
  238. writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
  239. #endif
  240. da8xx_configure_lpsc_items(lpsc, lpsc_size);
  241. /* GPIO setup */
  242. board_gpio_init();
  243. #if !CONFIG_IS_ENABLED(DM_SERIAL)
  244. NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
  245. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  246. #endif
  247. /*
  248. * Fix Power and Emulation Management Register
  249. * see sprufw3a.pdf page 37 Table 24
  250. */
  251. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  252. DAVINCI_UART_PWREMU_MGMT_UTRST),
  253. #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
  254. &davinci_uart0_ctrl_regs->pwremu_mgmt);
  255. #else
  256. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  257. #endif
  258. #if defined(CONFIG_SYS_DA850_DDR_INIT)
  259. da850_ddr_setup();
  260. #endif
  261. return 0;
  262. }