init.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2012 Stephen Warren
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <dm/device.h>
  12. #include <fdt_support.h>
  13. #ifdef CONFIG_ARM64
  14. #include <asm/armv8/mmu.h>
  15. static struct mm_region bcm283x_mem_map[] = {
  16. {
  17. .virt = 0x00000000UL,
  18. .phys = 0x00000000UL,
  19. .size = 0x3f000000UL,
  20. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  21. PTE_BLOCK_INNER_SHARE
  22. }, {
  23. .virt = 0x3f000000UL,
  24. .phys = 0x3f000000UL,
  25. .size = 0x01000000UL,
  26. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27. PTE_BLOCK_NON_SHARE |
  28. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  29. }, {
  30. /* List terminator */
  31. 0,
  32. }
  33. };
  34. static struct mm_region bcm2711_mem_map[] = {
  35. {
  36. .virt = 0x00000000UL,
  37. .phys = 0x00000000UL,
  38. .size = 0xfe000000UL,
  39. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  40. PTE_BLOCK_INNER_SHARE
  41. }, {
  42. .virt = 0xfc000000UL,
  43. .phys = 0xfc000000UL,
  44. .size = 0x03800000UL,
  45. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  46. PTE_BLOCK_NON_SHARE |
  47. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  48. }, {
  49. /* List terminator */
  50. 0,
  51. }
  52. };
  53. struct mm_region *mem_map = bcm283x_mem_map;
  54. /*
  55. * I/O address space varies on different chip versions.
  56. * We set the base address by inspecting the DTB.
  57. */
  58. static const struct udevice_id board_ids[] = {
  59. { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
  60. { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
  61. { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
  62. { },
  63. };
  64. static void _rpi_update_mem_map(struct mm_region *pd)
  65. {
  66. int i;
  67. for (i = 0; i < 2; i++) {
  68. mem_map[i].virt = pd[i].virt;
  69. mem_map[i].phys = pd[i].phys;
  70. mem_map[i].size = pd[i].size;
  71. mem_map[i].attrs = pd[i].attrs;
  72. }
  73. }
  74. static void rpi_update_mem_map(void)
  75. {
  76. int ret;
  77. struct mm_region *mm;
  78. const struct udevice_id *of_match = board_ids;
  79. while (of_match->compatible) {
  80. ret = fdt_node_check_compatible(gd->fdt_blob, 0,
  81. of_match->compatible);
  82. if (!ret) {
  83. mm = (struct mm_region *)of_match->data;
  84. _rpi_update_mem_map(mm);
  85. break;
  86. }
  87. of_match++;
  88. }
  89. }
  90. #else
  91. static void rpi_update_mem_map(void) {}
  92. #endif
  93. unsigned long rpi_bcm283x_base = 0x3f000000;
  94. int arch_cpu_init(void)
  95. {
  96. icache_enable();
  97. return 0;
  98. }
  99. int mach_cpu_init(void)
  100. {
  101. int ret, soc_offset;
  102. u64 io_base, size;
  103. rpi_update_mem_map();
  104. /* Get IO base from device tree */
  105. soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
  106. if (soc_offset < 0)
  107. return soc_offset;
  108. ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
  109. &io_base, &size);
  110. if (ret)
  111. return ret;
  112. rpi_bcm283x_base = io_base;
  113. return 0;
  114. }
  115. #ifdef CONFIG_ARMV7_LPAE
  116. void enable_caches(void)
  117. {
  118. dcache_enable();
  119. }
  120. #endif