spl_atmel.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Atmel Corporation
  4. * Bo Shen <voice.shen@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/at91_common.h>
  11. #include <asm/arch/at91_pit.h>
  12. #include <asm/arch/at91_pmc.h>
  13. #include <asm/arch/at91_rstc.h>
  14. #include <asm/arch/at91_wdt.h>
  15. #include <asm/arch/clk.h>
  16. #include <spl.h>
  17. static void switch_to_main_crystal_osc(void)
  18. {
  19. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  20. u32 tmp;
  21. tmp = readl(&pmc->mor);
  22. tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff);
  23. tmp &= ~AT91_PMC_MOR_KEY(0xff);
  24. tmp |= AT91_PMC_MOR_MOSCEN;
  25. tmp |= AT91_PMC_MOR_OSCOUNT(8);
  26. tmp |= AT91_PMC_MOR_KEY(0x37);
  27. writel(tmp, &pmc->mor);
  28. while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
  29. ;
  30. #if defined(CONFIG_SAMA5D2)
  31. /* Enable a measurement of the external oscillator */
  32. tmp = readl(&pmc->mcfr);
  33. tmp |= AT91_PMC_MCFR_CCSS_XTAL_OSC;
  34. tmp |= AT91_PMC_MCFR_RCMEAS;
  35. writel(tmp, &pmc->mcfr);
  36. while (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINRDY))
  37. ;
  38. if (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINF_MASK))
  39. hang();
  40. #endif
  41. tmp = readl(&pmc->mor);
  42. /*
  43. * some boards have an external oscillator with driving.
  44. * in this case we need to disable the internal SoC driving (bypass mode)
  45. */
  46. #if defined(CONFIG_SPL_AT91_MCK_BYPASS)
  47. tmp |= AT91_PMC_MOR_OSCBYPASS;
  48. #else
  49. tmp &= ~AT91_PMC_MOR_OSCBYPASS;
  50. #endif
  51. tmp &= ~AT91_PMC_MOR_KEY(0xff);
  52. tmp |= AT91_PMC_MOR_KEY(0x37);
  53. writel(tmp, &pmc->mor);
  54. tmp = readl(&pmc->mor);
  55. tmp |= AT91_PMC_MOR_MOSCSEL;
  56. tmp &= ~AT91_PMC_MOR_KEY(0xff);
  57. tmp |= AT91_PMC_MOR_KEY(0x37);
  58. writel(tmp, &pmc->mor);
  59. while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS))
  60. ;
  61. #if !defined(CONFIG_SAMA5D2)
  62. /* Wait until MAINRDY field is set to make sure main clock is stable */
  63. while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY))
  64. ;
  65. #endif
  66. #if !defined(CONFIG_SAMA5D4) && !defined(CONFIG_SAMA5D2)
  67. tmp = readl(&pmc->mor);
  68. tmp &= ~AT91_PMC_MOR_MOSCRCEN;
  69. tmp &= ~AT91_PMC_MOR_KEY(0xff);
  70. tmp |= AT91_PMC_MOR_KEY(0x37);
  71. writel(tmp, &pmc->mor);
  72. #endif
  73. }
  74. __weak void matrix_init(void)
  75. {
  76. /* This only be used for sama5d4 soc now */
  77. }
  78. __weak void redirect_int_from_saic_to_aic(void)
  79. {
  80. /* This only be used for sama5d4 soc now */
  81. }
  82. /* empty stub to satisfy current lowlevel_init, can be removed any time */
  83. void s_init(void)
  84. {
  85. }
  86. void board_init_f(ulong dummy)
  87. {
  88. int ret;
  89. switch_to_main_crystal_osc();
  90. #ifdef CONFIG_SAMA5D2
  91. configure_2nd_sram_as_l2_cache();
  92. #endif
  93. #if !defined(CONFIG_WDT_AT91)
  94. /* disable watchdog */
  95. at91_disable_wdt();
  96. #endif
  97. /* PMC configuration */
  98. at91_pmc_init();
  99. at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
  100. matrix_init();
  101. redirect_int_from_saic_to_aic();
  102. timer_init();
  103. board_early_init_f();
  104. mem_init();
  105. ret = spl_init();
  106. if (ret) {
  107. debug("spl_init() failed: %d\n", ret);
  108. hang();
  109. }
  110. preloader_console_init();
  111. }