spl_at91.c 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 DENX Software Engineering
  4. * Heiko Schocher <hs@denx.de>
  5. *
  6. * Based on:
  7. * Copyright (C) 2013 Atmel Corporation
  8. * Bo Shen <voice.shen@atmel.com>
  9. */
  10. #include <common.h>
  11. #include <hang.h>
  12. #include <init.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/at91_common.h>
  15. #include <asm/arch/at91sam9_matrix.h>
  16. #include <asm/arch/at91_pit.h>
  17. #include <asm/arch/at91_rstc.h>
  18. #include <asm/arch/at91_wdt.h>
  19. #include <asm/arch/clk.h>
  20. #include <spl.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static void enable_ext_reset(void)
  23. {
  24. struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  25. writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
  26. }
  27. void lowlevel_clock_init(void)
  28. {
  29. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  30. if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
  31. /* Enable Main Oscillator */
  32. writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
  33. /* Wait until Main Oscillator is stable */
  34. while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
  35. ;
  36. }
  37. /* After stabilization, switch to Main Oscillator */
  38. if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
  39. unsigned long tmp;
  40. tmp = readl(&pmc->mckr);
  41. tmp &= ~AT91_PMC_CSS;
  42. tmp |= AT91_PMC_CSS_MAIN;
  43. writel(tmp, &pmc->mckr);
  44. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  45. ;
  46. tmp &= ~AT91_PMC_PRES;
  47. tmp |= AT91_PMC_PRES_1;
  48. writel(tmp, &pmc->mckr);
  49. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  50. ;
  51. }
  52. return;
  53. }
  54. void __weak matrix_init(void)
  55. {
  56. }
  57. void __weak at91_spl_board_init(void)
  58. {
  59. }
  60. void __weak spl_board_init(void)
  61. {
  62. }
  63. void board_init_f(ulong dummy)
  64. {
  65. #if CONFIG_IS_ENABLED(OF_CONTROL)
  66. int ret;
  67. ret = spl_early_init();
  68. if (ret) {
  69. debug("spl_early_init() failed: %d\n", ret);
  70. hang();
  71. }
  72. #endif
  73. lowlevel_clock_init();
  74. #if !defined(CONFIG_WDT_AT91)
  75. at91_disable_wdt();
  76. #endif
  77. /*
  78. * At this stage the main oscillator is supposed to be enabled
  79. * PCK = MCK = MOSC
  80. */
  81. at91_pllicpr_init(0x00);
  82. /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
  83. at91_plla_init(CONFIG_SYS_AT91_PLLA);
  84. /* PCK = PLLA = 2 * MCK */
  85. at91_mck_init(CONFIG_SYS_MCKR);
  86. /* Switch MCK on PLLA output */
  87. at91_mck_init(CONFIG_SYS_MCKR_CSS);
  88. #if defined(CONFIG_SYS_AT91_PLLB)
  89. /* Configure PLLB */
  90. at91_pllb_init(CONFIG_SYS_AT91_PLLB);
  91. #endif
  92. /* Enable External Reset */
  93. enable_ext_reset();
  94. /* Initialize matrix */
  95. matrix_init();
  96. gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
  97. /*
  98. * init timer long enough for using in spl.
  99. */
  100. timer_init();
  101. /* enable clocks for all PIOs */
  102. #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
  103. at91_periph_clk_enable(ATMEL_ID_PIOAB);
  104. at91_periph_clk_enable(ATMEL_ID_PIOCD);
  105. #else
  106. at91_periph_clk_enable(ATMEL_ID_PIOA);
  107. at91_periph_clk_enable(ATMEL_ID_PIOB);
  108. at91_periph_clk_enable(ATMEL_ID_PIOC);
  109. #endif
  110. #if defined(CONFIG_SPL_SERIAL_SUPPORT)
  111. /* init console */
  112. at91_seriald_hw_init();
  113. preloader_console_init();
  114. #endif
  115. mem_init();
  116. at91_spl_board_init();
  117. }