timer.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <time.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/at91_pit.h>
  13. #include <asm/arch/clk.h>
  14. #include <div64.h>
  15. #if !defined(CONFIG_AT91FAMILY)
  16. # error You need to define CONFIG_AT91FAMILY in your board config!
  17. #endif
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /*
  20. * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  21. * setting the 20 bit counter period to its maximum (0xfffff).
  22. * (See the relevant data sheets to understand that this really works)
  23. *
  24. * We do also mimic the typical powerpc way of incrementing
  25. * two 32 bit registers called tbl and tbu.
  26. *
  27. * Those registers increment at 1/16 the main clock rate.
  28. */
  29. #define TIMER_LOAD_VAL 0xfffff
  30. /*
  31. * Use the PITC in full 32 bit incrementing mode
  32. */
  33. int timer_init(void)
  34. {
  35. at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
  36. at91_periph_clk_enable(ATMEL_ID_SYS);
  37. /* Enable PITC */
  38. writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  39. gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
  40. return 0;
  41. }
  42. /*
  43. * Return the number of timer ticks per second.
  44. */
  45. ulong get_tbclk(void)
  46. {
  47. return gd->arch.timer_rate_hz;
  48. }