ast2500-board.c 1.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <ram.h>
  9. #include <timer.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/timer.h>
  12. #include <asm/arch/wdt.h>
  13. #include <linux/err.h>
  14. #include <dm/uclass.h>
  15. /*
  16. * Second Watchdog Timer by default is configured
  17. * to trigger secondary boot source.
  18. */
  19. #define AST_2ND_BOOT_WDT 1
  20. /*
  21. * Third Watchdog Timer by default is configured
  22. * to toggle Flash address mode switch before reset.
  23. */
  24. #define AST_FLASH_ADDR_DETECT_WDT 2
  25. DECLARE_GLOBAL_DATA_PTR;
  26. void lowlevel_init(void)
  27. {
  28. /*
  29. * These two watchdogs need to be stopped as soon as possible,
  30. * otherwise the board might hang. By default they are set to
  31. * a very short timeout and even simple debug write to serial
  32. * console early in the init process might cause them to fire.
  33. */
  34. struct ast_wdt *flash_addr_wdt =
  35. (struct ast_wdt *)(WDT_BASE +
  36. sizeof(struct ast_wdt) *
  37. AST_FLASH_ADDR_DETECT_WDT);
  38. clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
  39. #ifndef CONFIG_FIRMWARE_2ND_BOOT
  40. struct ast_wdt *sec_boot_wdt =
  41. (struct ast_wdt *)(WDT_BASE +
  42. sizeof(struct ast_wdt) *
  43. AST_2ND_BOOT_WDT);
  44. clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
  45. #endif
  46. }
  47. int board_init(void)
  48. {
  49. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  50. return 0;
  51. }
  52. int dram_init(void)
  53. {
  54. struct udevice *dev;
  55. struct ram_info ram;
  56. int ret;
  57. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  58. if (ret) {
  59. debug("DRAM FAIL1\r\n");
  60. return ret;
  61. }
  62. ret = ram_get_info(dev, &ram);
  63. if (ret) {
  64. debug("DRAM FAIL2\r\n");
  65. return ret;
  66. }
  67. gd->ram_size = ram.size;
  68. return 0;
  69. }