systick-timer.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ARM Cortex M3/M4/M7 SysTick timer driver
  4. * (C) Copyright 2017 Renesas Electronics Europe Ltd
  5. *
  6. * Based on arch/arm/mach-stm32/stm32f1/timer.c
  7. * (C) Copyright 2015
  8. * Kamil Lulko, <kamil.lulko@gmail.com>
  9. *
  10. * Copyright 2015 ATS Advanced Telematics Systems GmbH
  11. * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
  12. *
  13. * The SysTick timer is a 24-bit count down timer. The clock can be either the
  14. * CPU clock or a reference clock. Since the timer will wrap around very quickly
  15. * when using the CPU clock, and we do not handle the timer interrupts, it is
  16. * expected that this driver is only ever used with a slow reference clock.
  17. *
  18. * The number of reference clock ticks that correspond to 10ms is normally
  19. * defined in the SysTick Calibration register's TENMS field. However, on some
  20. * devices this is wrong, so this driver allows the clock rate to be defined
  21. * using CONFIG_SYS_HZ_CLOCK.
  22. */
  23. #include <common.h>
  24. #include <init.h>
  25. #include <time.h>
  26. #include <asm/io.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
  29. #define SYSTICK_BASE 0xE000E010
  30. struct cm3_systick {
  31. uint32_t ctrl;
  32. uint32_t reload_val;
  33. uint32_t current_val;
  34. uint32_t calibration;
  35. };
  36. #define TIMER_MAX_VAL 0x00FFFFFF
  37. #define SYSTICK_CTRL_EN BIT(0)
  38. /* Clock source: 0 = Ref clock, 1 = CPU clock */
  39. #define SYSTICK_CTRL_CPU_CLK BIT(2)
  40. #define SYSTICK_CAL_NOREF BIT(31)
  41. #define SYSTICK_CAL_SKEW BIT(30)
  42. #define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF
  43. /* read the 24-bit timer */
  44. static ulong read_timer(void)
  45. {
  46. struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
  47. /* The timer counts down, therefore convert to an incrementing timer */
  48. return TIMER_MAX_VAL - readl(&systick->current_val);
  49. }
  50. int timer_init(void)
  51. {
  52. struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
  53. u32 cal;
  54. writel(TIMER_MAX_VAL, &systick->reload_val);
  55. /* Any write to current_val reg clears it to 0 */
  56. writel(0, &systick->current_val);
  57. cal = readl(&systick->calibration);
  58. if (cal & SYSTICK_CAL_NOREF)
  59. /* Use CPU clock, no interrupts */
  60. writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl);
  61. else
  62. /* Use external clock, no interrupts */
  63. writel(SYSTICK_CTRL_EN, &systick->ctrl);
  64. /*
  65. * If the TENMS field is inexact or wrong, specify the clock rate using
  66. * CONFIG_SYS_HZ_CLOCK.
  67. */
  68. #if defined(CONFIG_SYS_HZ_CLOCK)
  69. gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
  70. #else
  71. gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
  72. #endif
  73. gd->arch.tbl = 0;
  74. gd->arch.tbu = 0;
  75. gd->arch.lastinc = read_timer();
  76. return 0;
  77. }
  78. /* return milli-seconds timer value */
  79. ulong get_timer(ulong base)
  80. {
  81. unsigned long long t = get_ticks() * 1000;
  82. return (ulong)((t / gd->arch.timer_rate_hz)) - base;
  83. }
  84. unsigned long long get_ticks(void)
  85. {
  86. u32 now = read_timer();
  87. if (now >= gd->arch.lastinc)
  88. gd->arch.tbl += (now - gd->arch.lastinc);
  89. else
  90. gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now;
  91. gd->arch.lastinc = now;
  92. return gd->arch.tbl;
  93. }
  94. ulong get_tbclk(void)
  95. {
  96. return gd->arch.timer_rate_hz;
  97. }